The other ESS DACS - ES9006 (Premier) and ES9016 (Ultra)

I'm thinking to do a 9006 build as well as a 9023 build (in small quantities the 9006 is actually slightly lower cost per channel than the 9023 even if you don't use all the channels). The 9006 and 9016 are pin compatible except for ADDR/AUTOMUTE so, allowing for minor microcontroller and power supply differences, a board for one can easily accommodate the other much like one board can support both the 9008 and 90018.

Not much discussion of these parts here on DIYA. Anyone done a build with them? Any A/B testing of them against the other ESS DACs? Anyone found audible differences between the 9006/9008 or 9016/9018 which trace back to the DAC rather than supporting components such as supply or output buffers or differences in DAC configuration such as changing the filter coefficients?

Just curious. If we can share knowledge it might save a few folks proto spins.

So, my 90x6 DAC project's been on hold for some time due to summer and a bunch of power amplifier design work I've been doing. I've recently had time to get back to it and would like input on the clocking. The board I'm working on consists of an ADAU1445 SigmaDSP part feeding the DAC in 8 channel mode via I2S. Input will initially be via the SigmaDSP's SPDIF input but may eventually switch to a direct I2S input to the SigmaDSP.

The SigmaDSP parts require passing SPDIF input through an ASRC to manage the clock domain transition and then the DAC's FIR oversampling filters perform an additional ASRC operation. There's nothing unusual about this---just about all SPDIF receivers and most DACs resample---but the SigmaDSP's ability to operate at 44.1/48/88.2/96/176.4/192 along with the DACs' acceptance of clocks between 8.4672 and 50MHz (9006) or 100MHz (9016) allow many configuations. The most flexible way of clocking the system would be programming a clock generator to generate whatever clocks are desired for the SigmaDSP, DAC, and I2S sources, trying various configurations until an optimum's found.

However, I'm thinking this may be overkill. I've already resampled various recordings (all 44.1 redbook) to 48, 88.2, and 96 using a variety of ASRCs such as SoX, Secret Rabbit, and the hardware in my Focusrite Saffire 40. My preference is to stay with 44.1, though I found 88.2 with slow rolloff filters (-mb 90 or -l, for example) offered a bit better tonality in slow passages without too much degradation of transients. 48 was pretty much uniformly awful, 96 was OK-ish but noticeably worse than 88.2. I therefore suspect I'll end up operating the SigmaDSP at 44.1 and the DAC at its maximum synchronous clock rate of 45.1584 or 90.3168MHz to minimize the duration of its FIR oversampling filters' transient response (ESS's 9016 and 9018 block diagrams show the oversampling filter's fed by MCLK; the same presumably holds for 9006, 9008, and 9022/9023). This admits the simpler solution of a 4x clock multiplier between the SigmaDSP and DAC, using frequencies of 11.2896 and 45.1584MHz with the 9006 and 22.5792 and 90.3168MHz with the 9016. Saves a few bucks on parts and the time to program up a microcontroller to configure a clock synthesizer.

For those who've tried various ESS DAC clocking options, how does this fit in with your experience? I'm assuming operating the 9016 in OSF bypass is a non-starter as ESS recommends upsampling by 8x while the best my Squeezebox or the SigmaDSP can do is is 4x.

jean-paul said:

I am on the ADP151 route myself and thought the opamps solution ESS suggest worth trying out. I now see that it is not ideal.

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I think it depends on how much effort one wants to put into the supply.

ESS's published AVcc data is for the 9008 and only goes to 50MHz, at which frequency the AVcc draw is 36mA. That's doable with an LME49720 or similar with one channel supplying the DAC's left supply and the other supplying the right supply; 18mA per channel's a bit harder than I'd choose to push the op amp but it's 5mA under National's min output current spec.

Extrapolating ESS's data to 100MHz suggests the draw on AVcc would be 57mA typ. An LME49726 can supply this without much fuss. The GBP, open loop gain, and PSRR are about 20dB less than a 49720/49722/49725 but they're still probably higher than the ADP151 and the 49726 is lower noise. I don't believe the 49726 datasheet when it says the part can push 350mA from a 5V rail with 0V of drop but it's certainly going to be able to move 30+mA per channel from a 5V supply to a 3.3V output. What's less clear is what the output impedance would be and how much cap would required to ensure stabilization. The cap's no big deal---if a large MLCC doesn't do then a polymer electrolytic will---but I would guess the closed loop output impedance is 100mOhm up to maybe an Ohm. That's a little on the high side but to be sure one would need to build a test coupon and measure the part. Also, I haven't done a survey to see if there are other low noise, high current, voltage feedback op amps which might work better in this role. (All the high current op amps I know off the top of my head are current feedback and at least an order of magnitude noisier.)

In comparison, the ADP150 and 151 are turnkey to design to; since they're intended as regulators all the necessary info's in the datasheet. Throw a low ESR, low ESL 470uF polymer electrolytic on the output and the noise will be comparable to ESS's LME497x0 + 47uF MLCC arrangement. And the regulation probably as good or better (the output impedance peak moves down to 20kHz or so but reduces to something like 15mOhm). PSRR/ripple rejection's a bit lower but if all one does is LM7805 + ADP151 it's not hard to hold the ripple on AVcc to 100nV. That's comparable to the noise floor so I doubt it'd matter.

VDD_L and VDD_R are specific to the 64 pin DACs; they don't exist on the 9006 and 9016.

Do you have a link to your measurements of different reference topologies? ESS's approach of putting DVdd through a 1Hz lowpass seems fine given correct layout.

I thought that might be the case but wasn't entirely sure. Sounds like an oscope may not be the best choice for what you want to do; they're optimized for speed rather than detail and hence usually struggle with signals below a few millivolts. Consider a signal analyzer in addition or instead, though you'll find ones with the ability to make meaningful measurements of 19 and 20 bit DACs aren't cheap (or at least I'm not aware of lower cost alternatives to the Audio Precision units which have comparable resolution). A HP 3562A or similar can be had for quite a bit less than the APs and is quiet enough to measure noise floors and such. You're likely to hit problems with THD/IMD measurements though. For example, the 3562A has about 90dB dynamic range. So mostly one ends up measuring the instrument's own spurs. Also, be aware working with 120+dB ranges takes considerable attention to detail in the test and measurement setup to get good data. The last time I measured 100nV levels on an unshielded PCB it took shielded probe leads, turning off all the lights, and rearranging a significant portion of the workbench to remove noise sources---the laptop for data collection got sent to the other side of the room.

Interesting idea. A linear measurement amp could help in exposing the noise floor. But that's not that big of a deal---in addition to a sig an most 6.5 digit multimeters can do it (I've always thought it'd be cool to have a nanovoltmeter though). I'm not seeing any good way to make an amp nonlinear in a controlled fashion such that it'd assist in exposing the IMD floor. National uses a distortion booster to characterize the LME parts---see any of the op amp datasheets---but the approach is specific to the op amp's own input error.

Another way of looking at it is ESS's published data for the 9008 indicates DNR is limited by the op amps in the output buffer. So, from that perspective, if you want to maximize DNR you use LME49990s (quietest audio op amp around), do the best layout you can, and it is what it is. In some ways actually measuring the performance is irrelevant, though it's certainly desirable to have the cross check to verify you didn't do something on the PCB that's preventing the parts from hitting speced performance.

My working assumption has always been the 9006 is essentially the same die as the 9008 and the 9016 the same as the 9018. There's maybe a cost reduction on the 90x6 parts to only use one DAC per output instead of the dual DACs on the 90x8---I'm unsure if that'd result in enough of a die shrink to be worthwhile---but given Dustin's indication he optimized for output performance at the expense of PSRR I suspect the dominant factor is the reduction in package size as the 90x6 performance figures are consistently about 8dB worse than the 90x8s. The 48 pin DACs have only one AVCC pin per side and a single ground net (seven pins) instead of four AGNDs per side and four digital GNDs. Wouldn't surprise me if the metalization layers on the die don't change and the part's simply bonded out differently. Another interesting thing is the 9006 datasheet shows only a voltage mode output buffer. I've probed Brian Shaw (ESS's US distributor) about this and he simply ducked the question. That makes me curious if the 9006 datasheet lists the part's voltage mode performance and whether one would observe a performance improvement similar to the 9008 by operating it current mode. I've also asked how the 9016 was characterized and gotten no answers about its eval board. But it seems reasonable to assume the datasheet figures were obtained by using the same output buffer and supply configurations as used with the 9008, 9012, and 9018. What op amps the eval was done with is anyone's guess, but since the 9016 is at a lower price point it's more likely 2134s, 5534s, or 49710s were used than 49990s or 797s.

This implies the datasheet numbers on the 9016 (124dB DNR, -110dB THD) are about as good as the part gets, though one might be able to get THD down by a couple dB. The 9006 might come in as speced (120dB DNR, -102dB THD) but it might be able to hit -110dB THD in a current mode configuration. -110dB is about the noise floor of my Focusrite Saffire 40 at lower frequencies (though there's a few dB bump at the mains frequency and it worsens to -100ish at 20kHz)---and loopback testing's shown the THD/IMD floor is below the noise floor. So, combined with an RTA or record + analyze in offline software, the Saffire beats a 3562A for measuring distortion and has just enough performance to reasonably check the 90x6 DACs' linearity. I also expect to operate the output buffers at 6dB gain, implying a best case noise floor of -114dB. So my plan for the 90x6 board is to have a look with the Saffire and see if I can see anything. If I can't, eh, mission accomplished. (A friend's 6.5 digit DMM can check if I'm missing the last couple dB of DNR but, IMO, it's not worth the money to spin the board for a couple dB.)

One reason I'm interested in the 90x6 parts is I suspect there's no audible difference between them and the 90x8s in a playback system with reasonably structured gains. That speculation's based, in part, on my experience with the LME49710, LME49713, and LME49990. I can measure the noise floor difference between these parts but everything else is beyond the ability of my gear or other gear I have access to in both the electrical and acoustic domains (no top end Audio Precions, though). I gave up trying to find a subjective difference between the parts as in blind A/B I had no idea which part was which. So I now default to the 49710 or the other 497xx parts with comparable performance---no real reason to incur the noise floor lift of the 49713 or the cost riser for the 49990.

It's hard to beat the top end ESS parts on DNR because of the large number of parallel DACs (16per channel in the case of the 9012) but the noise floor on a 49710's lower than either of the 90x6 parts. It's not hard to beat the ESS DACs on THD as 497xx parts are more linear. While it's very difficult to hit this level of performance in a discrete implementation a fully integrated DAC to power amp topology is capable of up to 65W into 6 ohms while operating an ESS part in current mode with a single 497xx and a Darlington pair between the DAC and the speaker driver. It's usually more convenient to use two op amps---one to buffer the DAC output for the interconnect to the power amp and one for the power amp's control loop---and the THD and electrical noise floor remain limited by the output devices and noise (the acoustic noise floor's usually the refrigerator, heating/cooling, wind, or street noise, though since ears are directive one can listen under it to a certain extent). Power BJTs are fairly quiet and an LME based control loop has pretty good loop gain---70dB or more at 20kHz---so, depending on the load, the performance ranges from not much worse than the DAC at tens of watts to a few watts down to better than the DAC when the output device can be an AD8017 or LME49600 (the AD8397 and LMH6321 are only slightly noisier). There's also the headphone case where all that's needed is the DAC's output buffer.

Incidentally, those four chips are all worth considering if one wants good performance with output current than typical op amps provide.

I would be surprised if the 9006 and 9016 and the 9008 and 9012/9018 are the same chips. If you look at the 9008 thread Dustin accumulates a few incremental adjustments to make and the analog performance numbers do improve slightly on the 901x parts. In the previous post I was referring to similarity between the 9006 and 9008---the v1 parts if you will---and the 9016 and 9018---which are more of a v1.1.

It's been about six months since the last post on this thread. So I suppose a project update is in order. To summarize, ESS DACs get a lot of attention because of the low THD and high DNR specs of their flagship parts. The lower end of ESS's lineup---the ES9006 and ES9016---has headline specs comparable to the Cirrus codecs often used in pro audio and the Wolfson flagship DACs popular in hi-fi. As a number of previous posts in this thread touch on, the primary motivation for pushing THD and DNR is poor SnR downstream of the DAC. Typically this is due to a mismatch between playback levels and power amp gain and, from a design standpoint, is most easily addressed by lowering the amp's gain. Mostly this matters when crossover is done in DSP and volume control is done either by scaling the DAC's inputs or within the DAC itself (in preamp based topologies performance generally limits on the volume control chip or, in the case of a passive pre, noise and impedance matching, though typical power amp gains are demanding of the rest of the system as well). A corollary of this is that, at least in playback systems with a reasonable gain structure, attention to power supplies, and so on, once a DAC hits -100dB THD and 100+dB DNR it's quite probably functionally interchangeable in that regard with any other DAC having equivalent or better headline specs.

This prompted me to look at other considerations. ESS does not do well on basics such as availability of design collateral and parts. But I was eventually able to get through to ESS and get two white papers which fill in some missing pieces as to how ESS's ASRC based jitter rejection works (though you can figure out about 95% of it from the patents) and how the antialiasing filters are implemented. As with the rest of ESS's design documents these are delivered on request and watermarked for the recipient so it's not appropriate to repost them here. However, I can share my design status.

The antialiasing filters built into ESS's parts are linear phase. The default fast rolloff filter is much the same as the linear phase "brickwalls" found on other DACs. ESS's slow rolloff has a noticeably wider transition band than the slow roll linear phase filters chosen by other manufacturers and hence is a good choice if one is attempting to minimize the amount of preringing the antialiasing filter creates in the output signal. However, after doing a variety of ABX trials with similar filters I found the filter's impulse response was audible with just about 100% discrimination. Intermediate phase filters with reduced preringing scored better, though not as well as minimum phase filters. Since ESS's built in filters are all linear phase this means the only compete option ESS has against Cirrus and Wolfson in this regard is for one to synthesize one's own minimum phase-ish filter and program it into an ES901x series DAC. This is somewhat interesting for the control it offers but, in practice, it means you can maybe pick slightly different tradeoffs than Cirrus and Wolfson did and then do quite a bit of optimization work to make your filter as good as the turnkey options available in other parts. So, from a pragmatic perspective, I found myself asking what advantage a $27 ES9016 offers compared to a $11.50 CS42528. For my intended use cases the 9016 does not look attractive in comparison---more expensive, harder to get, harder to use, and most likely no meaningful advantage in jitter reduction.

That bit about jitter probably needs some explanation. 250ps period jitter is typical of basic SPDIF clock recovery or low end clock generators. This implies a 20kHz floor of -86dB minus the jitter rejection provided by the DAC’s DEM. The resulting performance will vary depending on DAC implementation and the jitter structure but the third party measurements ESS commissioned on competing DACs indicate one can expect around -98dB THD. For a DAC with headline performance of -100dB THD this is not much degradation. There will also be some reduction in DNR from jitter noise coupling into the DAC outputs but the measurements I’m finding show noise floors remaining below -119dB. The actual degradation dependss on DAC and PCB layout, power supply coupling, and so on but---loosely speaking---this would result in the loss of 1dB of DNR on an AK4399, ES9016, or WM8742 (dB unweighted, not dB-A) and be below the floor of an ES9006 or Cirrus’s 114dB DNR lineup. So, while one has to build it, measure it, and ABX it to be sure, from a design standpoint there doesn’t seem to be a case for a high end clock in a playback system with good gain structure. Part to part variation tends to be around 6dB so if you’re designing to -100dB THD/115dB DNR nominal you probably have to handle a -94dB/110dB corner anyway.

This is no bad thing. The SPDIF receive -> DSP crossover and EQ -> multichannel DAC signal flow I’ve been looking at in this thread is most simply implemented with a codec. The recovered clock never leaves the part so there’s no additive jitter in the DAC clock from buffering, PCB vagarities, and so on---it is emitted as the codec’s I2S bit clock and reflected back in the input streams to the codec but whatever core is performing the DSP is free to process samples asynchronously. This approach does not work well with the SigmaDSP parts I was considering at the start of this thread, which implement asynchronous processing via the same ASRC block used in the AD1896 and therefore impose the undesirable transient response ringing of a linear phase, fast rolloff, antialiasing filter each time a clock domain is crossed. The SGPIO slices on NXP’s LPC4300 Cortex M4/M0 parts have no such restriction plus the ARM parts are lower cost and simpler to implement. As a result, a two chip solution of a Cirrus CS425xx codec and LPC43x0 is therefore attractive---performance should be better than an ES9006 (inaudible THD and DNR differences, audible improvement from reduced preringing) on a lower cost and simpler board.

The next step up is a Wolfson WM880x SPDIF transceiver -> LPC4300 -> ES9016 chain. This approach should work with most DACs---WM8804 and WM8805 jitter is unlikely to rise above 55ps and locking the LPC4300’s PLL0AUDIO or PLL1 to the recovered clock minimizes additive jitter on the DAC MCLK emitted by the microcontroller. In the case of an ESS part performance is determined by the DPLL bandwidth which provides optimum jitter rejection while still reliably tracking the recovered clock. To understand the tradeoff one can refer to the initial publication of the DAC architecture later adopted by ESS by Bob Adams of Analog Devices in 1994 and the implementation results following in 1996. Analog implemented an improved version of this sample and hold ASRC in the AD1955 but, as the 1996 paper points out, deriving a more stable DAC output clock from the input MCLK with a DPLL results in output jitter of one MCLK period with sample and hold which has to be noise shaped out of band. ESS reduces the induced jitter by using the DPLL phase to provide a first order interpolation of the transitional sample’s value and in one of the ES9022 threads here on DIY Audio Dustin Forman remarks the part requires an MCLK of 1024Fs to fully shape the noise out of the audible band at a 44.1kHz sample rate (not spotting the link but it should turn up in a search of dusfor99’s posts---Dustin’s the design lead for the ESS DACs). As the maximum output clock of the WM880x is 512Fs the LPC4300 PLL should multiply by a factor of two to four for redbook audio to yield an MCLK in range of 45.1584 to 90.3168MHz for the ESS DAC. Wolfson does not state the bandwidth of their receivers’ PLLs but it appears to be 100Hz or lower. The LPC4300 PLLs have a 10kHz bandwidth so the jitter this configuration presents to the DPLL in the ESS DAC will primarily be the jitter of the receiver’s PLL. That should be amenable to lowpassing by the DAC’s DPLL. It’s difficult to estimate how much jitter will remain on the DAC’s output clock but I would not expect problems with getting the DPLL to lock and provide several dB of rejection. This should be all that’s needed to hit the ES9016’s internal limitations---20ps of jitter on the DPLL output implies a -120dB floor at 20kHz (prior to DEM jitter attenuation) and the part has -110dB THD and around 120dB DNR (dB again, not dB-A).

An alternative is the XO based MCLK first implemented on the AD1955 eval board, used with a crystal by ESS on their eval board, and implemented with an XO by AckoDAC, Twisted Pear, and others on ESS boards. A not particularly expensive XO yields around 26ps total jitter with the more expensive XO Twisted Pear uses on the Buffalo DAC coming in at perhaps a third of that. This is roughly a 6 to 14dB reduction from the 50ps period jitter of the WM880x. Potentially useful if one’s trying to get the most out of an ES9012 or ES9018 but probably overkill with a 9016 (or 9018) operating multichannel.

Unfortunately there’s a significant parts cost riser for adopting the ES9016 in order to be able to program minimum phase coefficients into one or both of the antialiasing filter stages. Plus cost or time in synthesizing and optimizing the Q31 filter coefficients. I find this makes alternative multichannel DACs such as the CS4365 attractive. The 10dB THD and DNR performance loss shouldn’t be significant (within the gain structure constraint mentioned above) but the difference in effort to synthesize antialiasing filters which look much like what you can get in a six dollar part is---buying a synthesis tool or coding the numerical methods for synthesis is straightforward but either runs a few hundred dollars or consumes a fair number of hours programming numerical methods. So I’ve opted to switch focus to designing a Cirrus codec board. This is somewhat unusual so far as DIY decisions go but happens to suit my interests.

MCLK Note: The DIY Audio community is split on the topic of ESS DAC MCLKs with some folks finding improvement from synchronous clocking and others simply saying clocks in the 80 to 100MHz range sound best. These statements do not seem to be based on measurement or blind tests in any of the threads I’ve looked at. The ASRC outputs one sample per MCLK and MCLK must be at least 256Fs. Upsampling by 256 or more minimizes the aliasing of the antialiasing filter’s impulse response which causes degradation in lower factor conversions such as upsampling from 44.1 to 96. As such, the primary MCLK design constraint I can find is Dustin’s remark about 1024Fs and noise shaping mentioned above. Dustin also mentions in another post that measured DAC performance improves only slightly as the clock rate is increased from 22MHz. While I linked a 100MHz Fox Xpresso above Xpressos are available at several other frequencies in the 24 to 100MHz range at low cost. Any of these should offer a reasonable cost/performance tradeoff between providing MCLK from a microcontroller and using one of National or TI’s jitter cleaning clock generators.

Linearity Note: ESS mentions improved state space control as an advantage of ESS DACs but it’s unclear exactly what parts the advantage is in respect to. DC offset results are in Martin Mallinson’s RMAF jitter talk (slide 36) and can be compared to parts like the WM8470 which are about 7dB tighter (figure 4). Unfortunately, if anyone’s published DC offset results for Cirrus parts I’ve been unable to find them.

tomchr said:

The noise floor of the PLL itself comes into play as well.

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Thanks for the reminder. I'd looked at AN339 some time ago but forgotten about it. Figures 7, 8, 12, and 14 in show the noise shaping into a 75kHz spur in fast phase detector update mode (see also figures 30 and 31 and the remarks on baseband jitter at the beginning of section 5). Based on the dates, datasheet remarks, and matching specs it seems reasonable to assume the new PLL mode in Cirrus's revision D codecs is the same fast phase detector update mode used on the CS8416. If that's correct the jitter when locked to a 60ps RMS jitter source at 44.1 should be right around the jitter spec in the codec datasheet---125ps of codec baseband jitter on top of 60ps RMS = 206ps RMS (baseband jitter is RMS, so root sum of squares). That would fall to somewhere around 60ps RMS + 60ps RMS = 85ps RMS at 96.

In theory it would be higher performance if the Cirrus codecs did the same jitter changeout with their OMCK that the WM880x do with their crystal. The measurement conditions for Wolfson's 50ps intrinsic jitter spec aren't stated in the datasheet but are contained in the screenshots of their SPDIF jitter app note, which shows 51ps RMS over 12288 samples of 12.288MHz clock. The sample rate is not specified but is likely 48kHz as that's what used for the other measurements in the app note and the part is specified at 48kHz Fs, 12.288MHz MCLK (256Fs) in the datasheet. Source terminate the part's CLKOUT pin, priority route the trace to a DAC, and I'd guess the resultant MCLK would be around 55ps RMS jitter. The I2S links from the SPDIF receiver to the microcontroller/DSC/DSP and then to the DAC carry their own clocks so likely no need to buffer MCLK---parts like the CS4365 have no requirement on the phase between MCLK and the input I2S bit clock.

If we assume the measurement jitter floor is negligible, the MCLK jitter distribution is Gaussian, and apply 66-95-99.7 it's probably reasonable to consider 600ps as an upper bound for the Cirrus codecs and 150ps for the Wolfson receivers (RMS jitter is one standard deviation). The Wolfsons fall within the -98dB 20kHz post-DEM floor I mentioned in my previous post for this thread but the Cirrus parts would probably be more like -95dB. Allow a few dB of process tolerance in the PLL and the worst case could easily fall outside the -94dB DAC corner.

However, the difference between the specs may be due to the measurement gear. Cirrus’s data is taken with an Audio Precision SYS-2722 and Wolfson’s with a LeCroy jitter scope. AP’s specs on the 2722 are vague as to its jitter floor but I interpret them to indicate the jitter floor is <0.0003 UI, which is 100ps for 64Fs 44.1 SPDIF and 50ps at 96. Since both AP’s spec and pulse spurs are inversely proportional to the SPDIF bit rate it’s not possible to disambiguate between the two but in the best case the baseband jitter on the codecs is 25ps for 44.1. Wolfson doesn’t indicate which LeCroy, but it appears to be one of the WaveMasters in which case the jitter floor’s 600fs or lower. So the Cirrus parts could be anywhere from 6dB better to 12dB worse than the WM880x. My guess is the 2722 Cirrus used beats its spec with a margin on the order of 20%, in which case the underlying performance would be about the same and the codecs’ performance limited by the DACs rather than clock recovery given a reasonably well behaved source.

This is assuming wired SPDIF and jitter from attaching the measurement gear being comparable to that from the cable actually in use, which is probably reasonable. I haven’t been able to find any measurements of the additive jitter from Toslink transreception but would assume it’s around 100ps. Plus something like 10ps/m for reflections in the cable. Probably also inaudible but it’d be interesting to see if one could get any discrimination in ABX or double blind testing. (Either way, one could probably make a tidy sum selling ultra black optical cables to audiophools for improved ambient light rejection. Does your stereo sound blue when it's cloudy? We can help! )

qusp said:

I do wonder why you are still futsing about with spdif?

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One could implement USB mass storage support on the LPC4300, hook up the LCD driver, and implement something much like a Squeezebox Touch. Or replace the crystal on a Squeezebox with a clock out from the DAC. Or implement one's own version of sample and hold. None of these are all that interesting to me---I get enough programming in my day job---but looking at SPDIF and PLLs is. Besides, if I put much more into this project it'd take me forever to get anywhere with it. So a SPDIF input's fine for now and the rest can be done in vNext if I find there's a statistically significant subjective degradation from the clock recovery.