Co-packaged optics (CPO): status, challenges, and solutions

FIONA: Photonic-Electronic CoSimulation Framework and Transferable Prototyping for Photonic Accelerator

RONet: Scaling GPU System with Silicon Photonic Chiplet

Smart Knowledge Transfer-based Runtime Power Management

Fast and Accurate Statistical Simulation of Shared-Memory Applications on Multicore Systems

HERO: Pbit High-Radix Optical Switch based on Integrated Silicon Photonics for Data Center

Improving the thermal reliability of photonic chiplets on multicore processors

A Reliability Concern on Photonic Neural Networks

Accelerating Cache Coherence in Manycore Processor through Silicon Photonic Chiplet

Energy-Efficient and Low-Cost Optical Neural Network

Energy-Efficient High-Performance Photonic Backplane Network for Rack-Scale Computing Systems

Improve the Stability and Robustness of Power Management through Model-free Deep Reinforcement Learning

PHANES: ReRAM-Based Photonic Accelerator for Deep Neural Networks

Power Management for Chiplet-Based Multicore Systems Using Deep Reinforcement Learning

Reduce Footprints of Multiport Interferometers by Cosine-Sine-Decomposition Unfolding

Reduce Loss and Crosstalk in Integrated Silicon-Photonic Multistage Switching Fabrics through Multichip Partition

Simultaneously Tolerate Thermal and Process Variations through Indirect Feedback Tuning for Silicon Photonic Networks

Multi-core Power Management Through Deep Reinforcement Learning

Rejuvenate Post-Moore's Law Computing with Photonics-Electronics Hybrid Systems

UONN: Energy-Efficient Optical Neural Network

A Cross-Layer Optimization Framework for Integrated Optical Switches in Data Centers

CAMON: Low-Cost Silicon Photonic Chiplet for Manycore Processors

Chip-Specific Power Delivery and Consumption Co-Management for Process Variation-Aware Manycore Systems Using Reinforcement Learning

Modeling and Analysis of Optical Modulators Based on Free-Carrier Plasma Dispersion Effect

Multi-Device Collaborative Power Management through Decentralized Knowledge Sharing

Multidomain Inter/Intrachip Silicon Photonic Networks for Energy-Efficient Rack-Scale Computing Systems

A Fast Joint Application-Architecture Exploration Platform for Heterogeneous Systems

Efficient Optical Power Delivery System for Hybrid Electronic-Photonic Manycore Processors

Collaborative Power Management through Knowledge Sharing Among Multiple Devices

Crosstalk noise reduction through adaptive power control in inter/intra-chip optical networks

Silicon photonics enabled rack-scale many-core systems

Decentralized Collaborative Power Management through Multi-Device Knowledge Sharing

Scalable low-power high-performance rack-scale optical network

Systematic exploration of high-radix integrated silicon photonic switches for datacenters

A Systematic and Realistic Network-on-chip Traffic Modeling and Generation Technique for Emerging Many-core Systems

Workload-aware adaptive power delivery system management for many-core processors

A Comprehensive Electro-Optical Model for Silicon Photonic Switches

Co-Manage Power Delivery and Consumption for Manycore Systems Using Reinforcement Learning

Cross-Layer Optimization for High-Radix Integrated Optical Switches in Data Centers

Lattice-matched metastable Zinc-blende MnSe1-xTex on ZnTe as a promising THz emitter material

Multi-device collaborative management through knowledge sharing

RSON: an Inter/Intra-Chip Silicon Photonic Network for Rack-scale Computing Systems

Alleviate Chip Pin Constraint for Multicore Processor by On/Off-Chip Power Delivery System Codesign

Energy-Efficient Power Delivery System Paradigms for Many-Core Processors

High-Radix Nonblocking Integrated Optical Switching Fabric for Data Center

Photonic Interconnects for Computing Systems: Understanding and Pushing Design Challenges

Introduction

Unified inter-and intra-chip optical interconnect networks

Adaptive power delivery system management for many-core processors with on/off-chip voltage regulators

Comparisons of a Novel Optical Space Switch and AWGR

Fast and Accurate Exploration of Multi-Level Caches Using Hierarchical Reuse Distance

MOCA: an Inter/Intra-Chip Optical Network for Memory

Thermal-sensitive design and power optimization for a 3D torus-based optical NoC

A Holistic Modeling and Analysis of Optical-Electrical Interfaces for Inter/Intra-chip Interconnects

An Adaptive Process-Variation-Aware Technique for Power-Gating-Induced Power/Ground Noise Mitigation in MPSoC

Coherent and Incoherent Crosstalk Noise Analyses in Interchip/Intrachip Optical Interconnection Networks

Distributed Sensor Network-on-Chip for Performance Optimization of Soft-Error-Tolerant Multiprocessor System-on-Chip

Improve Chip Pin Performance Using Optical Interconnects

Low-Loss High-Radix Integrated Optical Switch Networks for Software-Defined Servers

Inter/intra-chip Optical Interconnection Network: Opportunities, Challenges, and Implementations

JADE: a Heterogeneous Multiprocessor System Simulation Platform Using Recorded and Statistical Application Models

Panel discussions “computing and communication evolution for IoT innovations”

Actively Alleviate Power-Gating-Induced Power/Ground Noise Using Parasitic Capacitance of On-Chip Memories in MPSoC

An Analytical Study of Power Delivery Systems for Many-Core Processors Using On-Chip and Off-Chip Voltage Regulators

An Inter/Intra-Chip Optical Network for Manycore Processors

Crosstalk Noise in WDM-Based Optical Networks-on-Chip: A Formal Study and Comparison

Fat-Tree-Based Optical Interconnection Networks Under Crosstalk Noise Constraint

Adaptively Tolerate Power-Gating-Induced Power/Ground Noise under Process Variations

Alleviate Chip I/O Pin Constraints for Multicore Processors through Optical Interconnects

CLAP: a crosstalk and loss analysis platform for optical interconnects

Coherent crosstalk noise analyses in ring-based optical interconnects

Memory Access Analysis of Many-core System with Abundant Bandwidth

A Case Study of Signal-to-Noise Ratio in Ring-Based Optical Networks-on-Chip

Floorplan Optimization of Fat-Tree-Based Networks-on-Chip for Chip Multiprocessors

On-chip sensor networks for soft-error tolerant real-time multiprocessor systems-on-chip

SUOR: Sectioned Undirectional Optical Ring for Chip Multiprocessor

Systematic Analysis of Crosstalk Noise in Folded-Torus-Based Optical Networks-on-Chip

System-Level Modeling and Analysis of Thermal Effects in WDM-Based Optical Networks-on-Chip

UNION: A Unified Inter/Intrachip Optical Network for Chip Multiprocessors

A Case Study on the Communication and Computation Behaviors of Real Applications in NoC-based MPSoCs

A systematic network-on-chip traffic modeling and generation methodology

Characterizing power delivery systems with on/off-chip voltage regulators for many-core processors

Holistic Modeling and Comparison of Inter-Chip Optical and Electrical Interconnects

Introduction to the special session on “Silicon photonic interconnects: an illusion or a realistic solution?”

On the Impact of Crosstalk Noise in Optical Networks-on-Chip

3-D Mesh-Based Optical Network-on-Chip for Multiprocessor System-on-Chip

A formal study on topology and floorplan characteristics of mesh and torus-based optical networks-on-chip

Five-Port Optical Router Based on Microring Switches for Photonic Networks-on-Chip

Formal Worst-Case Analysis of Crosstalk Noise in Mesh-Based Optical Networks-on-Chip

On-Chip Sensor Network for Efficient Management of Power Gating-Induced Power/Ground Noise in Multiprocessor System on Chip

System-Level Modeling and Analysis of Thermal Effects in Optical Networks-on-Chip

A Network-on-Chip Benchmark Suite Based on Real Applications

Active power-gating-induced power/ground noise alleviation using parasitic capacitance of on-chip memories

System-level Analysis of Mesh-based Hybrid Optical-Electronic Network-on-Chip

A Torus-Based Hierarchical Optical-Electronic Network-on-Chip for Multiprocessor System-on-Chip

Crosstalk noise analysis and optimization in 5 × 5 hitless silicon-based optical router for optical networks-on-chip (ONOC)

FONoC: a Fat Tree Based Optical Network-on-Chip for Multiprocessor System-on-Chip

A novel low-waveguide-crossing floorplan for fat tree based optical networks-on-chip

Holistic comparison of optical routers for chip multiprocessors

Thermal analysis for 3D optical network-on-chip based on a novel low-cost 6x6 optical router

Coroutine-based synthesis of efficient embedded software from SystemC models

Elimination of cross-talk in silicon-on-insulator waveguide crossings with optimized angle

Novel RD-Optimized VBSME with Matching Highly Data Re-Usable Hardware Architecture

Power Gating Aware Task Scheduling in MPSoC

Satisfiability Modulo Graph Theory for Task Mapping and Scheduling on Multiprocessor Systems

A NoC traffic suite based on real applications

Modeling and Analysis of Thermal Effects in Optical Networks-on-Chip

Sub-pixel downsampling of video with matching highly data re-use hardware architecture

A new distributed congestion control mechanism for networks on chip

Design of butterfly-fat-tree optical network on-chip

Simultaneous OTDM demultiplexing and data format conversion using A D flip-flop

Integrated Microsystems: MEMs, Bio and Photonics Interfaces

A hardware-software collaborated method for soft-error tolerant MPSoC

A Hierarchical Hybrid Optical-Electronic Network-on-Chip

A Highly Data Reusable and Standard-Compliant Motion Estimation Hardware Architecture

A low power and standard-compliant RDO motion estimation hardware architecture for VBSME

Crosstalk noise and bit error rate analysis for optical network-on-chip

Performance evaluation of on-chip sensor network (SENoC) in MPSoC

Simulation and Analysis of P/G Noise in TSV based 3D MPSoC

UNION: A Unified Inter/Intra-Chip Optical Network for chip multiprocessors

Double-Data-Rate, Wave-Pipelined Interconnect for Asynchronous NoCs

Efficient algorithms for 2D area management and online task placement on runtime reconfigurable FPGAs

Efficient Software Synthesis for Dynamic Single Appearance Scheduling of Synchronous Dataflow

3D Optical Networks-on-chip (NoC) for Multiprocessor Systems-on-chip (MPSoC)

A case study of on-chip sensor network in multiprocessor system-on-chip

A low-power fat tree-based optical Network-On-Chip for multiprocessor system-on-chip

A Low-power Low-cost Optical Router for Optical Networks-on-Chip in Multiprocessor Systems-on-Chip

A novel multiple description video coding based on H.264/AVC video coding standard

An efficient technique for analysis of minimal buffer requirements of synchronous dataflow graphs with model checking

Design of 3D Optical Network on Chip

On-line MPSoC scheduling considering power gating induced power/ground noise

Reducing Wavelength Conversion Range in Space/Wavelength Switches

A novel optical mesh network-on-chip for gigascale systems-on-chip

Design ASNoC for Low-Power SoCs

Design of sparse mesh for optical network on chip

ODOR: A microresonator-based high-performance low-cost router for optical networks-on-chip

A design methodology for application-specific networks-on-chip

A methodology for design, modeling, and analysis of networks-on-chip

H.264 HDTV Decoder Using Application-Specific Networks-on-Chip

A methodology for architectural design of multimedia multiprocessor SoCs

MPSoCs for Video

A case study in networks-on-chip design for embedded video

Augmenting Platform-based Design with Synthesis Tools

A wave-pipelined on-chip interconnect structure for networks-on-chips

Platform-Based Design and the First Generation Dilemma

Wave pipelining for application-specific networks-on-chips

A Systematic and Realistic Network-on-chip Traffic Modeling and Generation Technique for Emerging Many-core Systems

Article

Workload-aware adaptive power delivery system management for many-core processors

Article

A Comprehensive Electro-Optical Model for Silicon Photonic Switches

Conference paper

Co-Manage Power Delivery and Consumption for Manycore Systems Using Reinforcement Learning

Conference paper

Cross-Layer Optimization for High-Radix Integrated Optical Switches in Data Centers

Conference paper

Lattice-matched metastable Zinc-blende MnSe1-xTex on ZnTe as a promising THz emitter material

Conference paper

Multi-device collaborative management through knowledge sharing

Conference paper

RSON: an Inter/Intra-Chip Silicon Photonic Network for Rack-scale Computing Systems

Conference paper

Alleviate Chip Pin Constraint for Multicore Processor by On/Off-Chip Power Delivery System Codesign

Article

Energy-Efficient Power Delivery System Paradigms for Many-Core Processors

Article

High-Radix Nonblocking Integrated Optical Switching Fabric for Data Center

Article

Photonic Interconnects for Computing Systems: Understanding and Pushing Design Challenges

Book

Introduction

Book chapter

Unified inter-and intra-chip optical interconnect networks

Book chapter

Adaptive power delivery system management for many-core processors with on/off-chip voltage regulators

Conference paper

Comparisons of a Novel Optical Space Switch and AWGR

Conference paper

Fast and Accurate Exploration of Multi-Level Caches Using Hierarchical Reuse Distance

Conference paper

MOCA: an Inter/Intra-Chip Optical Network for Memory

Conference paper

Thermal-sensitive design and power optimization for a 3D torus-based optical NoC

Conference paper

A Holistic Modeling and Analysis of Optical-Electrical Interfaces for Inter/Intra-chip Interconnects

Article

An Adaptive Process-Variation-Aware Technique for Power-Gating-Induced Power/Ground Noise Mitigation in MPSoC

Article

Coherent and Incoherent Crosstalk Noise Analyses in Interchip/Intrachip Optical Interconnection Networks

Article

Distributed Sensor Network-on-Chip for Performance Optimization of Soft-Error-Tolerant Multiprocessor System-on-Chip

Article

Improve Chip Pin Performance Using Optical Interconnects

Article

Low-Loss High-Radix Integrated Optical Switch Networks for Software-Defined Servers

Article

Inter/intra-chip Optical Interconnection Network: Opportunities, Challenges, and Implementations

Conference paper

JADE: a Heterogeneous Multiprocessor System Simulation Platform Using Recorded and Statistical Application Models

Conference paper

Panel discussions “computing and communication evolution for IoT innovations”

Conference paper

Actively Alleviate Power-Gating-Induced Power/Ground Noise Using Parasitic Capacitance of On-Chip Memories in MPSoC

Article

An Analytical Study of Power Delivery Systems for Many-Core Processors Using On-Chip and Off-Chip Voltage Regulators

Article

An Inter/Intra-Chip Optical Network for Manycore Processors

Article

Crosstalk Noise in WDM-Based Optical Networks-on-Chip: A Formal Study and Comparison

Article

Fat-Tree-Based Optical Interconnection Networks Under Crosstalk Noise Constraint

Article

Adaptively Tolerate Power-Gating-Induced Power/Ground Noise under Process Variations

Conference paper

Alleviate Chip I/O Pin Constraints for Multicore Processors through Optical Interconnects

Conference paper

CLAP: a crosstalk and loss analysis platform for optical interconnects

Conference paper

Coherent crosstalk noise analyses in ring-based optical interconnects

Conference paper

Memory Access Analysis of Many-core System with Abundant Bandwidth

Conference paper

A Case Study of Signal-to-Noise Ratio in Ring-Based Optical Networks-on-Chip

Article

Floorplan Optimization of Fat-Tree-Based Networks-on-Chip for Chip Multiprocessors

Article

On-chip sensor networks for soft-error tolerant real-time multiprocessor systems-on-chip

Article

SUOR: Sectioned Undirectional Optical Ring for Chip Multiprocessor

Article

Systematic Analysis of Crosstalk Noise in Folded-Torus-Based Optical Networks-on-Chip

Article

System-Level Modeling and Analysis of Thermal Effects in WDM-Based Optical Networks-on-Chip

Article

UNION: A Unified Inter/Intrachip Optical Network for Chip Multiprocessors

Article

A Case Study on the Communication and Computation Behaviors of Real Applications in NoC-based MPSoCs

Conference paper

A systematic network-on-chip traffic modeling and generation methodology

Conference paper

Characterizing power delivery systems with on/off-chip voltage regulators for many-core processors

Conference paper

Holistic Modeling and Comparison of Inter-Chip Optical and Electrical Interconnects

Conference paper

Introduction to the special session on “Silicon photonic interconnects: an illusion or a realistic solution?”

Conference paper

On the Impact of Crosstalk Noise in Optical Networks-on-Chip

Conference paper

3-D Mesh-Based Optical Network-on-Chip for Multiprocessor System-on-Chip

Article

A formal study on topology and floorplan characteristics of mesh and torus-based optical networks-on-chip

Article

Five-Port Optical Router Based on Microring Switches for Photonic Networks-on-Chip

Article

Formal Worst-Case Analysis of Crosstalk Noise in Mesh-Based Optical Networks-on-Chip

Article

On-Chip Sensor Network for Efficient Management of Power Gating-Induced Power/Ground Noise in Multiprocessor System on Chip

Article

System-Level Modeling and Analysis of Thermal Effects in Optical Networks-on-Chip

Article

A Network-on-Chip Benchmark Suite Based on Real Applications

Conference paper

Active power-gating-induced power/ground noise alleviation using parasitic capacitance of on-chip memories

Conference paper

System-level Analysis of Mesh-based Hybrid Optical-Electronic Network-on-Chip

Conference paper

A Torus-Based Hierarchical Optical-Electronic Network-on-Chip for Multiprocessor System-on-Chip

Article

Crosstalk noise analysis and optimization in 5 × 5 hitless silicon-based optical router for optical networks-on-chip (ONOC)

Article

FONoC: a Fat Tree Based Optical Network-on-Chip for Multiprocessor System-on-Chip

Book chapter

A novel low-waveguide-crossing floorplan for fat tree based optical networks-on-chip

Conference paper

Holistic comparison of optical routers for chip multiprocessors

Conference paper

Thermal analysis for 3D optical network-on-chip based on a novel low-cost 6x6 optical router

Conference paper

Coroutine-based synthesis of efficient embedded software from SystemC models

Article

Elimination of cross-talk in silicon-on-insulator waveguide crossings with optimized angle

Article

Novel RD-Optimized VBSME with Matching Highly Data Re-Usable Hardware Architecture

Article

Power Gating Aware Task Scheduling in MPSoC

Article

Satisfiability Modulo Graph Theory for Task Mapping and Scheduling on Multiprocessor Systems

Article

A NoC traffic suite based on real applications

Conference paper

Modeling and Analysis of Thermal Effects in Optical Networks-on-Chip

Conference paper

Sub-pixel downsampling of video with matching highly data re-use hardware architecture

Conference paper

A new distributed congestion control mechanism for networks on chip

Article

Design of butterfly-fat-tree optical network on-chip

Article

Simultaneous OTDM demultiplexing and data format conversion using A D flip-flop

Article

Integrated Microsystems: MEMs, Bio and Photonics Interfaces

Book chapter

A hardware-software collaborated method for soft-error tolerant MPSoC

Conference paper

A Hierarchical Hybrid Optical-Electronic Network-on-Chip

Conference paper

A Highly Data Reusable and Standard-Compliant Motion Estimation Hardware Architecture

Conference paper

A low power and standard-compliant RDO motion estimation hardware architecture for VBSME

Conference paper

Crosstalk noise and bit error rate analysis for optical network-on-chip

Conference paper

Performance evaluation of on-chip sensor network (SENoC) in MPSoC

Conference paper

Simulation and Analysis of P/G Noise in TSV based 3D MPSoC

Conference paper

UNION: A Unified Inter/Intra-Chip Optical Network for chip multiprocessors

Conference paper

Double-Data-Rate, Wave-Pipelined Interconnect for Asynchronous NoCs

Article

Efficient algorithms for 2D area management and online task placement on runtime reconfigurable FPGAs

Article

Efficient Software Synthesis for Dynamic Single Appearance Scheduling of Synchronous Dataflow

Article

3D Optical Networks-on-chip (NoC) for Multiprocessor Systems-on-chip (MPSoC)

Conference paper

A case study of on-chip sensor network in multiprocessor system-on-chip

Conference paper

A low-power fat tree-based optical Network-On-Chip for multiprocessor system-on-chip

Conference paper

A Low-power Low-cost Optical Router for Optical Networks-on-Chip in Multiprocessor Systems-on-Chip

Conference paper

A novel multiple description video coding based on H.264/AVC video coding standard

Conference paper

An efficient technique for analysis of minimal buffer requirements of synchronous dataflow graphs with model checking

Conference paper

Design of 3D Optical Network on Chip

Conference paper

On-line MPSoC scheduling considering power gating induced power/ground noise

Conference paper

Reducing Wavelength Conversion Range in Space/Wavelength Switches

Article

A novel optical mesh network-on-chip for gigascale systems-on-chip

Conference paper

Design ASNoC for Low-Power SoCs

Conference paper

Design of sparse mesh for optical network on chip

Conference paper

ODOR: A microresonator-based high-performance low-cost router for optical networks-on-chip

Conference paper

A design methodology for application-specific networks-on-chip

Article

A methodology for design, modeling, and analysis of networks-on-chip

Conference paper

H.264 HDTV Decoder Using Application-Specific Networks-on-Chip

Conference paper

A methodology for architectural design of multimedia multiprocessor SoCs

Article

MPSoCs for Video

Book chapter

A case study in networks-on-chip design for embedded video

Conference paper

Augmenting Platform-based Design with Synthesis Tools

Article

A wave-pipelined on-chip interconnect structure for networks-on-chips

Conference paper

Platform-Based Design and the First Generation Dilemma

Conference paper

Wave pipelining for application-specific networks-on-chips

Conference paper