Chip Industry Technical Paper Roundup: May 13
2D-TMD tunnel-FETs; AI-optimized FPGAs; modeling content addressable memories; LLM for synthesis errors; materials for high-temp; synthesis of goldene; modeling thermal crosstalk for photonics.
New technical papers added to Semiconductor Engineering’s library this week.
| Technical Paper | Research Organizations |
|---|---|
| Cross-layer Modeling and Design of Content Addressable Memories in Advanced Technology Nodes for Similarity Search | Georgia Tech |
| An ultra energy-efficient hardware platform for neuromorphic computing enabled by 2D-TMD tunnel-FETs | University of California Santa Barbara |
| Efficient Approaches for GEMM Acceleration on Leading AI-Optimized FPGAs | University of Texas at Austin and Arizona State University |
| Explaining EDA synthesis errors with LLMs | University of New South Wales and University of Calgary |
| Materials for High Temperature Digital Electronics | University of Pennsylvania, Air Force Research Laboratory, and Ozark Integrated Circuits |
| Synthesis of goldene comprising single-atom layer gold | Linköping University |
| Thermal Crosstalk Modelling and Compensation Methods for Programmable Photonic Integrated Circuits | Technical University of Denmark and iPronics Programmable Photonics |
More Reading
Technical Paper Library home
Tags: Air Force Research Laboratory Arizona State University Georgia Tech iPronics Programmable Photonics Linköping University Ozark Integrated Circuits Technical University of Denmark UC Santa Barbara University of Calgary University of New South Wales University of Pennsylvania UT Austin
Linda Christensen
(all posts)Linda Christensen is vice president of operations and a contributing writer at Semiconductor Engineering.
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