The FinFET: A Tutorial

Abstract

Ever since Intel launched its successful 22-nm Ivy Bridge CPU chip, establishing nonplanar finFET technology as a viable means of extending Moore’s law, variations of the basic finFET or the nanowire transistor have been introduced into nanoelectronics research and manufacturing efforts at an unprecedented rate.

All members of the finFET family of devices—whether fabricated on a bulk or SOI substrate, or structured as a double- or triple-gate or a nanowire transistor—share the same fundamental operating mechanism: the electric field effect. Drain current is under the control of a gate voltage that modulates the conductivity of the underlying fin or nanowire. This tutorial derives qualitative I-V characteristics for such devices, using intuitive assumptions and principles like Ohm’s law and Poisson’s equation.

It then focuses on the geometric characteristics of nonplanar devices, examining the layout of a typical CMOS standard cell comprising both n- and p-type finFETs. The use of a local interconnect layer to connect adjacent fins is detailed. A section is devoted to explaining why nonplanar devices exhibit higher immunity to short-channel effects (SCEs). To quantify this explanation, the natural screening length parameter λ is introduced and then computed for several common device types.

The tutorial cites a dozen intuitive rules of thumb that engineers and scientists may find useful in evaluating finFET design issues and device trade-offs. During the discussion, key electrical and physical finFET properties are related to their corresponding BSIM-CMG SPICE parameters, including GEOMOD and NFIN.

These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

2.1 Beyond Planar Technology

One of the most notable hand-drawn graphs in the world of technology was the logarithmic plot tacked to a wall of Gordon Moore’s office at Fairchild in Silicon Valley [1]. It revealed a trend: MOS integrated circuits doubled in complexity each year. A chemical engineer by training , Moore realized that no real physical barriers stood in the way of cramming more and more transistors onto a single die—unlike the thermodynamic equilibria conditions that can limit yield in chemical reactions. Achieving greater density and higher speed was just a matter of finer patterning [2].

Since 1965, Moore’s law has held for nearly five decades. Chip companies like Intel have progressed from the first 4004 microprocessor, with just 2,300 MOS transistors, to processors like the Xeon , with 7 billion on one die—just by scaling down device length, width, and other process parameters by ~√2 each year or two.

What has complicated the scaling, and threatened to upset Moore’s law, is a set of unwanted side effects, collectively known as short-channel effects (SCEs). SCEs arise from shrinking the channel length and other critical parameters. In 1965, the shortest commercial MOSFET had a channel length L of about 1 mil, or 25 μm. By 2011, Intel was planning to announce its Ivy Bridge CPU , with a length of 22 nm—10³× shorter. To circumvent the SCEs, they chose to go beyond planar technology.

Figure 2.1 is a conceptual view of a traditional short-channel nMOS transistor. (Advanced aspects, like LDD extensions or halo doping, are omitted for simplicity.) While the channel length L has been scaled down aggressively, the junction depth r_j of the source or drain has not scaled down as readily. One reason is the higher sheet resistance of shallow source-drain islands, limiting the drive current. Another is the inevitable diffusion of implanted dopant atoms during the fabrication process.

Fig. 2.1

Short-channel n-type MOSFET (side view)

As a result, the short-channel transistor is no longer very planar. This is evident in Fig. 2.1. The depth of the source-drain islands (r_j) is now comparable to the length L. Since these n-type islands form p-n junctions with the p-type substrate, they are surrounded by depletion regions of significant depth (d). The shorter the device, the more these depletion regions tend to encroach into the channel area underneath the gate. (For simplicity, the figure shows depletion regions of uniform depth, which assumes the source-drain voltage V_DS is small compared to VDD, and the transistor is operating in the linear region. SCEs worsen at higher drain bias.)

For older, long-channel transistors, the gate electrode effectively controlled the buildup of depletion charge (dashed rectangular outline in the figure). For shorter channels, with more encroachment, the gate lost control of some of this charge (shaded triangles). This shaded fraction of depletion charge needs no gate voltage to build up—it originates from the p-n junctions at the source and drain terminals.

What in 1965 was a rectangular volume of depletion charge under gate control (equal to −qN_AWLd_max, where N_A is the substrate doping) has in recent years become trapezoidal. As L shrinks, the shaded portions of the rectangle grow more significant. The undesirable result is that the transistor turns on at a lower gate voltage V_GS. The threshold voltage V_Tn is no longer determined only by processing parameters like N_A but instead decreases—rolls off—with shorter device length L .

Threshold voltage roll-off is one of the worst SCEs, in the sense that it directly impedes Moore’s law. Further scaling down of L can only be done at the expense of process enhancements that keep threshold voltages from rolling off excessively.

Figure 2.1 indicates another SCE. The yellow arrows superimposed on the figure occur when V_GS is just below threshold. Ideally, the transistor should turn off. In reality, there is a small drain current. It is due largely to electrons diffusing from the electron-rich source into the electron-poor p-type substrate and reaching the drain.

This subthreshold current will increase as L shrinks, since the channel is shorter compared to carrier diffusion length. The result is a parasitic current flow I_OFF which contributes to the chip’s static leakage power consumption in standby mode.

Consequently, by the 22-nm node, the traditional planar MOSFET had reached its limits. Scaling down L led to too much leakage, for too little performance boost. The most notorious of the SCEs impacting its operation are summarized below [3]:

• Threshold voltage roll-off : The threshold voltage, at which a transistor turns on, is no longer independent of gate length but rolls off with decreasing L.

• Subthreshold conduction : Just below threshold, the transistor never turns off entirely. A minuscule current flows, by the diffusion of carriers across the short channel. Though exponentially small, this subthreshold current—multiplied by billions of on-chip devices—leads to unacceptable levels of leakage power.

• Channel-length modulation : An early warning sign of SCEs, channel-length modulation (CLM) results in I-V curves that fail to saturate above pinch-off. The channel current I_DS continues to rise significantly with increased drain bias V_DS.

To circumvent these SCEs, and extend Moore’s law for a few more years, the semiconductor industry has departed from classic planar FET technology. In 2012, Intel launched its 22-nm Ivy Bridge CPU . Representing the most radical technology shift in five decades, this chip used a nonplanar transistor known as the finFET [4].

A finFET is built around a thin ridge of silicon, of order 100 nm in total height—like the dorsal fin on a fish’s back. Carriers flow from source to drain along this fin. In Sect. 2.3, we derive its first-order I-V characteristics. In Sect. 2.4, we look at its layout. In Sect. 2.5, we explore its short-channel behavior.

Before delving into the details, though, let us briefly look at a nonplanar device that is more symmetric and thus easier to understand at a conceptual level. In Sect. 2.2, we examine the basic operation of the nanowire field-effect transistor.

2.2 The Ideal Transistor

For purposes of maximizing control of the gate over the channel, and avoiding SCEs, the ultimate geometry for an MOS transistor is perhaps a silicon nanowire [5]. Figure 2.2 shows a conceptual view of an n-type nanowire FET. Its thickness (or diameter) is t_nw. Its length, from source to drain, is L. Its effective width, W_eff, is the wire’s circumference. Silicon nanowires can be fabricated by conventional MOS masking and etching on bulk wafers [6]. For simplicity, this figure omits such process-specific details as supporting silicon pillars at each end of the nanowire.

Fig. 2.2

Conceptual n-type nanowire FET (perspective view)

Because the gate electrode wraps all around the underlying silicon nanowire, the electrostatic control of V_GS over the drain-to-source current flow I_DS is maximal.

Encroachment by the source-drain depletion regions is minimal, and SCEs have less impact. Source-drain junction depth (r_j) plays less of a role. As a result, further scaling down of L can proceed more easily than in the traditional nMOS transistor.

2.2.1 Qualitative Behavior of a Nanowire

Let us investigate the qualitative behavior of this silicon nanowire (SNW) FET. By briefly examining this highly symmetric SNWFET, we will be better able to analyze the less-symmetric finFET structure, covered in detail in the next section.

As the applied gate voltage V_GS increases, the outer surface of the wire goes through three successive stages: accumulation, depletion, and inversion. We will focus mostly on the latter stage, in which the transistor is fully turned on, and a thin inversion layer of mobile electrons carries a current from the source to the drain.

It is natural to use cylindrical coordinates, as in the lower right corner of Fig. 2.2. Coordinate r is the radial distance to any point, perpendicular to the y-axis. The coordinate ϕ is the angle described as the radius sweeps out a full circle.

Clearly, this transistor is symmetric about the y-axis. Electrical conditions inside the nanowire—like inversion charge density—are independent of angle ϕ.

For tutorial purposes, we limit our discussion to thicker nanowires, in which the inversion charge resides in a thin layer at the surface of the wire, at a radius ½ t_nw. (Thin nanowires cannot be analyzed with the equations of classical physics alone, since electrons confined to nanoscale structures obey the laws of wave mechanics.)

Physical Insight: Quantum-Mechanical Effects

A truly small-geometry nanowire exhibits quantum-mechanical effects (QMEs). If the wire diameter t_nw is thin (say, below 10 nm), then electrons in the inversion layer are tightly confined in the radial (r) and angular (ϕ) directions. They are only free to drift along the axial direction y. Such localization leads to quantization [7].

The tightly confined electrons assert their wave nature and behave like a 1-D electron gas. This causes band splitting and volume inversion. Under volume inversion, the carriers can no longer be viewed as residing in a thin surface layer.

Small-geometry nanowires exhibiting QMEs are discussed in the literature [8]. Analysis starts by solving Poisson’s equation, in classical physics, to obtain the electrostatic potential Φ(r,y) for electrons within the wire. Substituting Φ into Schrödinger’s wave-mechanical equation yields the electron wave function ψ(r,y). The probability density |ψ|² is used to compute the concentration of electrons [9].

Now let us briefly investigate the three modes of nanowire transistor operation:

• 1. Accumulation : For V_GS less than 0 V, the gate has a negative charge. It is balanced by an equal and opposite positive charge on the wire, supplied by majority-carrier holes from the p-type interior. These holes accumulate near the surface. The channel region has an excess of holes—but few electrons. With no electrons to flow from n-type source to drain, the transistor is an open circuit.

• 2. Depletion : In this mode, V_GS is positive but still below the threshold voltage for an n-type device. Positive charge builds up on the gate, balanced by an equal and opposite negative charge on the nanowire. This negative charge arises as holes in the p-type wire are driven away from the positive gate. Each hole is filled with a valence electron, leaving a fixed, negatively-charged acceptor ion.

  Few electrons exist in the p-type wire under the gate. The wire surface is thus depleted of mobile carriers. The transistor is still an open circuit. We will denote this immobile, negative depletion-layer charge (per unit surface area) as Q_d(y).

• 3. Inversion : As V_GS exceeds the threshold voltage V_Tn for an n-type device, inversion sets in. Mobile conduction electrons flood into the nanowire from the source, until these minority carriers invert the original doping. The wire surface is now n-type instead of p-type. This thin inversion layer, a sleeve-like channel extending along the y-axis, forms a conducting bridge from source to drain. We will denote this mobile inversion channel charge (per unit surface area) as Q_i(y).

Figure 2.3 is a side view of the SNWFET. This cutaway view emphasizes that, during CMOS processing, the channel region inside the wraparound gate electrode remains lightly p-type or even undoped (intrinsic). Only the exposed source and drain regions are implanted heavily n-type (or p-type, for a complementary device). We assume for simplicity there are no trapped charges within the insulating oxide.

Fig. 2.3

Conceptual n-type nanowire FET (side view)

Our focus is inversion mode, when the SNWFET is fully turned on. Figure 2.4 is a qualitative plot of charge density along the inverted nanowire. Both components, Q_d and Q_i, are indicated. The profile shown is uniform along the entire y-axis. This uniform-channel condition exists if the drain bias V_DS is small compared to VDD.

Fig. 2.4

Charge profile inside nanowire FET

Both charge components will play a role in determining the I-V characteristics. The inversion charge density Q_i(y) consists of mobile electrons, residing as close to the nanowire surface as they can get. This corresponds to a radial distance ½ t_nw. The depletion charge density Q_d(y) is made up of N_A ionized acceptor ions per unit volume, at fixed sites throughout the lightly doped nanowire underneath the gate.

This depletion charge forms a layer of finite depth d. This depth depends upon process parameters such as ε_Si and N_A. (In a thin, lightly doped nanowire, the depth of depletion can reach ½ t_nw. Such a nanoscale structure is called fully depleted .)

In the next section, we briefly consider what happens at higher drain bias. Then the drain end of the nanowire is held at V_DS, while the source end is at 0 V. We will have to account for the variation of the inversion charge Q_i(y) and the depletion charge Q_d(y) as a function of the distance y from the source terminal.

2.2.2 Potential Distribution in a Nanowire

Even in as symmetric a structure as the SNWFET shown in Figs. 2.2 or 2.3, it is difficult to find the exact electric field distribution as a function of r and y. In this subsection, we explore the complexity of the problem. We then fall back upon the classic simplification known as the gradual-channel approximation (GCA) .

Instead of deriving the electric field, a vector, it is easier to find the electrostatic potential distribution Φ(r, ϕ, y), a scalar, related to the field by E = −∇Φ(r, ϕ, y).

In electrostatics, a scalar potential Φ arising from a distribution of charge obeys Poisson’s equation. Expressed in cylindrical coordinates, it takes the form of (2.1). By cylindrical symmetry, we can omit the derivative term with respect to the angle ϕ. The volume charge density qN_A on the RHS is applicable to the case of subthreshold operation, V_GS < V_Tn, in which the nanowire is depleted of carriers:

$$ \frac{\partial^2\Phi}{\partial {r}^2}+\frac{1}{r}\frac{\mathrm{\partial \Phi }}{\partial r}+\frac{1}{r^2}\frac{\partial^2\Phi}{\partial {\phi}^2}+\frac{\partial^2\Phi}{\partial {y}^2}=\frac{qN_A}{\varepsilon_{Si}} $$

(2.1)

This still leaves a partial differential equation in two variables, a complex task to solve analytically for Φ(r, y), unless we resort to simplifying assumptions [10].

To understand these simplifications, let us refer to Fig. 2.5, a conceptual plot of the potential profile Φ(r, y) inside the SNWFET, at a value of y between 0 and L. The vertical axis represents electrostatic potential. Working our way inward, we first see that the entire gate electrode is an equipotential region held at voltage V_GS.

Fig. 2.5

Potential profile inside nanowire FET

Inside the thin gate dielectric, Φ falls steadily as r decreases, corresponding to a relatively high electric field E_r. Inside the nanowire, Φ continues to fall. Its value at the very surface of the silicon—the surface potential—is denoted Φ_s. As part of the gradual-channel approximation, we assume that this silicon surface potential Φ_s remains relatively constant with rising gate bias V_GS once inversion is reached.

The surface potential is, however, directly affected by increasing drain bias V_DS. An applied drain bias raises the surface potential at a point y along the nanowire—especially toward the drain end. We thus replace Φ_s by the sum Φ_s + V(y), where V(y) reaches V_DS at the drain but is 0 V at the source. To first order, the increase is additive. This is valid under our assumption of a gradual channel, in which the field E_y and potential Φ(r, y) vary only gradually along y and where |E_r| > > |E_y|.

We will rely on this gradual-channel simplification in the subsections ahead, as we investigate the tri-gate finFET. In this subsection, our goal was to introduce the highly symmetric SNWFET, to better understand the less-symmetric finFET later.

The nanowire transistor is itself, however, the subject of intensive research and development. One issue still to be resolved is whether nanoscale wires, as they are scaled down further, can support adequate current flow for digital applications. Another issue is whether the surface roughness encountered by electrons in the inversion layer will be detrimental to their mobility. If these issues are resolved, SNWFETs could well become the future digital logic technology of choice.

Nanowire devices may also hold promise as on-chip sensors. Their nanoscale volume, ¼π(t_nw)²L, renders them highly sensitive to biochemical conditions, like minuscule variations in pH. Their transistor capabilities may enable such devices to combine an active sensing role with electrical amplification and conversion [11].

Physical Insight: Poisson’s Equation

Poisson’s equation is based upon Gauss’ law in differential form, which states: ε∇·E = ρ, for a volume charge density ρ in a medium of uniform permittivity ε. If the electric field is replaced with E = −∇Φ, where Φ is the electrostatic potential, then the result is a partial differential equation in three dimensions: ∇²Φ = − ρ/ε.

When applied to the charge distribution in a silicon substrate, nanowire, or fin, the electrical permittivity of crystalline silicon, ε_Si, must be used for ε. It is roughly 12ε₀, or 12× the permittivity of free space. The factor 12 is the relative dielectric constant. A key process parameter, the relative dielectric constant of the channel material, is represented in the BSIM-CMG model by the SPICE parameter EPSRSUB .

Though silicon is a semiconductor, and not a dielectric insulator, its permittivity enters into Poisson’s equation because the silicon lattice is highly polarizable. Any electric field arising from the charge distribution ρ is inevitably reduced because it polarizes the silicon atoms. The resulting atomic dipoles partially counteract E.

It is of historical interest to note that the differential equation developed by the French mathematician Poisson in 1813 is still in use two centuries later as the basis for modeling the most advanced MOS field-effect transistors, including nanowires.

In this section, we briefly investigated an almost ideal transistor, the SNWFET. Building on this conceptual groundwork, let us now examine a nonplanar transistor that is less ideal but is representative of devices already in production at foundries around the world. In the next section, we discuss the bulk tri-gate finFET device.

2.3 FinFET I-V Characteristics

All the members of the finFET family of devices —whether fabricated on a bulk or SOI substrate, or structured as a double- or triple-gate or a nanowire transistor—share one fundamental characteristic: their operating mechanism is the field effect. Drain current flow is under the control of a gate electrode that does not even touch the silicon substrate but—through the influence of a transverse electric field across the gate oxide—modulates the conductivity of the underlying fin or nanowire.

Figure 2.6 shows an n-type finFET on a bulk silicon substrate. Though generic, it is representative of devices already in production—such as Intel’s Ivy Bridge die tri-gate transistor [4]. The gate stack can be heavily doped or silicided polysilicon with an SiO₂ dielectric, or else an HKMG stack with a refractory metal gate using W, Ti, Mo, or their alloys [12]. For tutorial purposes, we assume the former, with an oxide capacitance (per unit area) of C_ox = ε_ox/t_ox. The silicon fin itself is integral to the underlying substrate. We will assume that it is lightly doped p-type.

Fig. 2.6

Generic bulk n-type finFET (perspective view)

For the rectangular finFET geometry of Fig. 2.6, it is natural to use the x-y-z coordinates at the lower right. Though not as symmetric as the nanowire transistor of Sect. 2.2, the finFET nevertheless behaves in a similar manner. The silicon fin of thickness t_fin plays a very similar role to that of the nanowire of diameter t_nw.

Let us derive qualitative I-V characteristics for this device, from first principles.

We seek to demonstrate that the current I_DS flowing through the fin is indeed controlled by the transverse electric field and hence by the applied gate voltage V_GS. It is also dependent on the applied drain voltage V_DS. We will again rely on the gradual-channel approximation (GCA) introduced in Sect. 2.2. We will bypass algebraic complexity, arriving at an intuitive description of finFET characteristics.

2.3.1 Uniform-Channel Conditions

The key observable in MOS transistors is the drain-to-source current I_DS as it varies with bias voltages V_GS and V_DS. The p-type substrate is assumed grounded. (Upper-case subscripts are used here to denote large-signal voltages and currents.)

As in our earlier analysis of the nanowire transistor, there are three finFET bias regions: accumulation, depletion, and inversion. To derive the I-V characteristics of a turned-on transistor, we focus on inversion. In this mode, the gate voltage V_GS exceeds the threshold voltage V_Tn for an n-type device. A positive charge builds up on the gate. It is balanced by an equal and opposite negative charge on the underlying fin. We will denote this total negative charge (per unit area) as Q_fin. As in Sect. 2.2, the negative fin charge arises from two independent contributions:

• 1. A layer of depth d of depletion charge Q_d (per unit area). It consists of acceptor atoms, at uniform concentration N_A throughout the fin, which have been ionized. This charge increases as the depletion layer deepens, exposing more acceptors.

• 2. A thin layer of inversion-channel charge Q_i (per unit area). It consists of mobile electrons flooding into the fin above threshold and residing close to its surfaces.

Summing up both these independent sources, the total negative charge (per unit area) above threshold, built up on all three exposed surfaces of the silicon fin, is:

$$ {Q}_{fin}={Q}_i+{Q}_d $$

(2.2)

We assume in this subsection that V_DS is small compared to the supply voltage VDD. Thus, charge densities do not vary significantly with y. Conditions along the length of the channel are uniform, from the source at y = 0 to the drain at y = L.

The silicon fin forms one plate of the capacitor. But not all of the applied gate voltage appears across the oxide dielectric. Some gate voltage is dropped between the surface of the fin and its interior. We again denote this surface potential as Φ_s:

$$ {V}_{GS}=\frac{-{Q}_{fin}}{C_{ox}}={\Phi}_s $$

(2.3)

For a uniform channel, we can assume that surface potential Φ_s is independent of y. Note that we ignore nonideal behavior, such as charges trapped in the oxide layer or at the fin interface. All of the fin charge is thus generated by the gate bias.

Rewriting (2.3), and substituting (2.2), we obtain the inversion charge density. For simplicity, we also ignore any process-specific differences in work functions:

$$ -{Q}_i={C}_{ox}\left[{V}_{GS}-{\Phi}_s\right]+{Q}_d $$

(2.4)

We rearrange (2.4) slightly to group together two terms in parentheses that are more dependent upon process parameters such as N_A than on the applied gate bias:

$$ -{Q}_i={C}_{ox}\left[{V}_{GS}-\left({\Phi}_s-{Q}_d/{C}_{ox}\right)\right] $$

(2.5)

As in subsection 2.2.2, we assume that Φ_s remains relatively constant as V_GS is increased, once inversion has been reached [13]. We can identify the parenthesized expression as a fixed threshold voltage, dependent on process parameters like N_A, ε_ox, and t_ox. When V_GS is at the threshold voltage for an n-type transistor, the charge Q_i is zero. To a first approximation, the threshold voltage can thus be expressed as:

$$ {V}_{Tn}={\Phi}_s-{Q}_d/{C}_{ox} $$

(2.6)

Using the expression in (2.6), we simplify (2.5) to obtain the inversion-channel charge (per unit area) Q_i. It is proportional to the gate voltage above threshold. Based on our assumption of a uniform channel, it does not vary appreciably with y:

$$ -{Q}_i={C}_{ox}\left[{V}_{GS}-{V}_{Tn}\right] $$

(2.7)

As V_GS increases further, above threshold, more negative charge must appear on the fin. Up to this threshold, the incremental charge was supplied by a deepening of the depletion layer, exposing more immobile ions. But Q_d grows slowly with gate bias, only as the square root. Above the threshold, the inversion charge Q_i grows exponentially with gate bias, flooding the fin with mobile electrons. It is this abrupt shift in the source of charge that leads to the concept of a threshold voltage V_Tn [14].

To first order, the depletion layer grows no deeper above threshold but remains fixed at a maximum depth d_max. This will simplify our analysis considerably. All of the second-order effects of depletion charge on I-V characteristics are lumped into a process-dependent parameter, the threshold voltage V_Tn. Depletion simply defers inversion, until V_GS exceeds a value largely determined by the substrate doping N_A.

Our simplification does have physical validity. In the limiting case of a fin that is fully depleted , Q_d does reach a limit, set by ½qN_At_fin. In exchange for simplicity, we sacrifice the ability to model SCEs. We are not accounting for the deepening of the depletion layer around the drain at higher V_DS and its encroachment on the channel. But our model is still adequate to yield qualitative finFET characteristics.

Based on this model, we can derive a useful rule of thumb. As electrons flood into the fin above V_Tn, they create a thin layer of inversion-channel charge (per unit area) Q_i. This conductive layer bridges the gap between the source and the drain.

The inversion electrons are mobile. Even under a small drain bias V_DS, they will drift along the channel in ohmic fashion, leaving the source and entering the drain. A microscopic form of Ohm’s law states that the average drift velocity of free electrons moving through a silicon lattice is directly proportional to the applied electric field. The proportionality constant μ_n is the electron mobility. Therefore:

$$ {\overline{v}}_y=-{\mu}_n{E}_y={\mu}_n\left|{E}_y\right| $$

(2.8)

The minus sign arises because electrons move against the electric field. On average, the drifting electrons will move from the source to the drain in a time interval τ. This transit time is just the length of the channel divided by the average velocity:

$$ \tau =\frac{L}{\mu_n\left|{E}_y\right|}=\frac{L^2}{\mu_n{V}_{DS}} $$

(2.9)

where the field ∣E_y∣is of the order of the drain bias V_DS over the channel length L.

It is this transit time τ that sets an inherent limit on the speed of the entire technology [15]. An n-type transistor in the pull-down network of a CMOS logic gate cannot discharge the load capacitance of the next gate any faster than the time it takes for the required charge to drift across the channel length L of the pull-down device. Though optimistic, this simple delay metric leads us to a first rule of thumb.

The transit time τ depends primarily on device length L . As device dimensions are scaled down by a factor of ~√2 from one technology node to the next, the density of gate logic on a silicon die scales up by a factor of 2. This is Moore’s law. But Eq. (2.9) suggests that the raw speed of the technology will increase by the same factor (partly offset by voltage scaling). This accounts for the industry-wide driving force behind decades of Moore’s law: scaling down channel length L—even at the cost of higher process complexity—enhances IC operating speed.

Rule of Thumb 1

For the nonplanar finFET, just as for planar MOSFETs, the inherent delay of the device decreases as the channel length L is scaled down—obeying Moore’s law.

In this subsection, under uniform-channel conditions, we can see from (2.8) that I_DS grows linearly with the field E_y and in turn with V_DS. At low drain bias, the ideal finFET thus behaves like a resistor. Here, low implies that V_DS is sufficient for current to flow yet small enough compared to V_GS that the drain bias does not yet affect the inversion charge Q_i. In the next subsection, we consider higher drain bias.

2.3.2 Gradual-Channel Conditions

Based on experimental I-V plots, we know that I_DS does not continue to increase linearly with V_DS. Instead, it will level off—or saturate. Because the drain end of the fin is held at V_DS, less of the applied gate bias will fall across the oxide there. Q_i will thin out near the drain. We must therefore modify Eq. (2.4) to account for the effect of V_DS on Q_i along the channel. We thus replace Q_i with Q_i(y). In the interests of simplicity, however, we will assume this charge variation is gradual.

Consider Fig. 2.7. Suppose that V_DS is 1.0 V. At one end of the fin, the source terminal, the drain bias is 0 V. There, the fin surface potential remains at the value Φ_s it had at threshold. At the other end, the drain terminal, the applied bias is V_DS. The surface potential there will be Φ_s + V_DS. At any intermediate point y along the fin, the surface potential must take on successive values, like those in the figure.

Fig. 2.7

Channel voltage along the fin (cutaway view)

The ohmic inversion layer, which bridges the gap between the source and drain, behaves in effect like a resistive capacitor plate [16]. We can now approximate the potential as a function of y. For a gradual channel, in which the gate bias has more influence on the inversion layer than does drain bias, we simply assume the effect is additive [17]. We replace potential Φ_s at the fin surface with the sum Φ_s + V(y).

Two boundary conditions must be satisfied at either end of this resistive plate: V(0) = 0 V at the source terminal and V(L) = V_DS at the drain terminal.

Replacing Φ_s in Eq. (2.4) with the sum Φ_s + V(y), we obtain a modified Eq. (2.10) for Q_i(y). Since V(y) must increase with y, the inversion charge will thin out toward the drain. This first-order approximation to the effects of drain bias on Q_i is comparable to the classic SPICE Level 1 model for a planar MOSFET:

$$ -{Q}_i(y)={C}_{ox}\left[{V}_{GS}-{\Phi}_s-V(y)\right]+{Q}_d $$

(2.10)

The potential inside the fin is, in reality, a function of the form Φ(x,y,z). It can only be found accurately by solving Poisson’s equation in three dimensions [18]. Advanced SPICE models, like BSIM-CMG Level 72, solve Poisson’s equation for a specific set of device parameters using sophisticated analytical approximations [19].

We will proceed, as in Subsection 2.3.1, to bypass mathematical complexities by treating Φ_s as constant above inversion. We thus lump all the second-order effects of depletion charge buildup into a fixed threshold voltage V_Tn. The approximate inversion-channel charge (per unit area) as a function of y for a gradual channel is:

$$ -{Q}_i(y)={C}_{ox}\left[{V}_{GS}-{V}_{Tn}-V(y)\right] $$

(2.11)

Equation (2.11) is only slightly more complex than (2.7). Let us reemphasize that (2.11) is strictly valid only for long-channel devices, under gradual-channel conditions. It cannot model SCEs. But it is adequate for deriving qualitative finFET characteristics and for demonstrating their dependence on IC process parameters.

Let us now compute the drain current I_DS flowing through this nonuniform, but gradual, channel. Consider an elemental cross section of the fin, as diagrammed in Fig. 2.8. During a steady-state flow, the current must be the same at any point y.

Fig. 2.8

Elemental channel cross section dy

The voltage drop V(y), however, increases along the channel. The differential voltage drop across this section is dV(y). The mobile inversion charge of (2.11) is spread in a thin layer over the three exposed surfaces of the fin (as indicated by tiny minus signs). The fixed depletion charge (circled minus signs) is indicated as well.

Only mobile charge contributes to the drain current. Recalling that Q_i denotes inversion charge per unit area, we can express the total mobile inversion charge on all three-fin surfaces, within this elemental volume, as dq = Q_i (2h_fin + t_fin) dy.

Since the carriers in an n-type device are negatively charged electrons, drifting along y from source to drain, let us first compute the source-to-drain current I_SD. The source-to-drain current flowing along y in the figure is the charge per unit time drifting through this fin cross section. Since dy/dt is the drift velocity, we get:

$$ {I}_{SD}=\frac{dq}{dt}=\frac{Q_i\left(2{h}_{fin}+{t}_{fin}\right) dy}{dt}={Q}_i\left(2{h}_{fin}+{t}_{fin}\right){\overline{v}}_y $$

(2.12)

From Eq. (2.8), the drift velocity is related to the lateral electric field E_y along the fin. But the y-component of the lateral field is the negative gradient of the potential V(y). With this substitution in (2.12), we get the differential equation:

$$ {I}_{SD}={\mu}_n\left(2{h}_{fin}+{t}_{fin}\right){Q}_i\frac{dV(y)}{dy} $$

(2.13)

Equation (2.13) describes drift current only. We neglect the diffusion current of these majority-carrier electrons; this is addressed by more sophisticated models [20]. We can now substitute (2.11) for Q_i(y). Reversing the sign to correspond to a conventional drain-to-source current, we arrive at the simple differential equation:

$$ {I}_{DS}={\mu}_n{C}_{ox}\left[{V}_{GS}-{V}_{Tn}-V(y)\right]\left(2{h}_{fin}+{t}_{fin}\right)\frac{dV(y)}{dy} $$

(2.14)

We can readily solve differential Eq. (2.14) by integrating over the entire length of the channel, from 0 to L. Let us multiply both sides by dy and then integrate:

$$ {I}_{DS}\underset{0}{\overset{L}{\int }} dy={\mu}_n\left(2{h}_{fin}+{t}_{fin}\right){C}_{ox}\underset{0}{\overset{V_{DS}}{\int }}\left[{V}_{GS}-{V}_{Tn}-V(y)\right] dV $$

(2.15)

We are thus summing differential voltage drops along the length L of the channel.

After integrating, we obtain the drain current in terms of bias voltages. This I-V characteristic is applicable to an n-type gradual-channel finFET above threshold, with an inversion layer that extends from source to drain (and is not pinched off). The resulting Eq. (2.16) is clearly an expression of the electric field effect:

$$ {I}_{DS}={\mu}_n{C}_{ox}\frac{\left(2{h}_{fin}+{t}_{fin}\right)}{L}\left[\left({V}_{GS}-{V}_{Tn}\right){V}_{DS}-\frac{1}{2}{V}_{DS}^2\right] $$

(2.16)

The gate voltage V_GS creates a transverse field across the oxide, described by E_x and E_z. This field modulates the conductivity of the fin. The degree of modulation depends on process parameters like the mobility μ_n and capacitance C_ox = ε_ox/t_ox.

An equation similar to (2.16) holds for complementary p-type finFET devices. In this case, positively charged holes flood into the inverted channel, forming a bridge from source to drain. We simply substitute hole mobility μ_p and the p-type device threshold V_Tp (a negative value), to obtain the I-V characteristic for p-type devices.

Figure 2.9 is a conceptual TCAD simulation of an n-type finFET, as it carries current. It shows the electron density, profiled at mid-channel, in a lightly doped 15-nm-thick rectangular fin. Such profiles are obtained using TCAD tools such as Synopsys Sentaurus Device [21]. Notice the high density at the three-fin surfaces.

Fig. 2.9

Conceptual TCAD profile of fin channel

In deriving the I-V characteristic of (2.16), we relied upon the gradual-channel approximation (GCA). This is accurate for long-channel devices. It loses validity for a short-channel device, in which the drain bias V_DS applied across a short channel L leads to high lateral field. Such a channel would no longer be gradual, and it would exhibit the same short-channel effects that were cited in Sect. 2.1.

It is important to realize, however, that—within its range of validity—the GCA model faithfully describes qualitative finFET behavior. Even sophisticated SPICE models for finFET devices—like the common-multigate BSIM-CMG algorithm—are founded upon a simplified core model. This core model typically starts from GCA assumptions [22]. This ensures the scalability of the model. The same algorithm can handle long-channel or short-channel finFETs, without encountering discontinuous currents or voltages—and without the need for artificial tuning parameters [23].

The current flow in (2.16) depends on channel length L, a layout parameter, just as it does for planar MOSFETs. Notice, however, a radical departure from planar technology: no layout parameter for channel width W appears in the equation. Instead, the finFET device has an effective width fixed by two process parameters:

$$ {W}_{eff}=\left(2{h}_{fin}+{t}_{fin}\right) $$

(2.17)

We can visualize the thin inversion layer as folded over the exposed fin surfaces. Its extent lies in two dimensions, x and z. The finFET is indeed a nonplanar device.

Rule of Thumb 2

The nonplanar finFET exhibits the same qualitative I_DS dependence on V_GS and V_DS as did the traditional planar MOSFET, under gradual-channel conditions, provided that the planar width W is replaced by the nonplanar effective width W_eff in (2.17).

This qualitative similarity has been borne out both by SPICE simulations and by experimental results [24]. Though its I-V characteristics, according to (2.16), follow the same first-order behavior as did the planar MOSFET, the nonplanar finFET is inherently more immune to SCEs. In Sect. 2.5, we will explore the reasons why.

Although we did not derive an I-V characteristic for the nanowire transistor of Sect. 2.2, it can be shown that it obeys, under GCA assumptions, an equation like (2.16)—except that its effective width is πt_nw, the nanowire’s circumference [25].

Equation (2.17) revealed that the width of a single-fin transistor is completely fixed by the fabrication process. But manual sizing of transistors is often critical to analog, and even standard-cell, designers, to meet difficult speed/power trade-offs. In Sect. 2.4, we will see how to adjust W_eff for an individual transistor by laying out multiple fins in parallel, and then tying them together electrically, in shunt.

Due to our simplifications, (2.17) ignores the potential corner effects [26] in a rectangular fin. The idealized fin of Fig. 2.6 has two sharp edges running along the y-axis. Just as electrostatic charge tends to accumulate at the tip of a teardrop-shaped conductor, any sharp fin edges and corners can lead to excessive channel charge density, accompanied by high electric fields, causing premature inversion.

We have ignored such edge effects by viewing the channel layer as folded over the fin. If the corner radius is not carefully controlled during fabrication, a tri-gate finFET can even exhibit two threshold voltages. The following insight outlines the common IC processing techniques used to mitigate the effects of sharp fin edges.

Physical Insight: Double-Gate Hard-Masked FinFETs

Sharp edges and corners can lead to parasitic inversion channels along the fin. One technique to avoid this problem is to fabricate a thick dielectric layer—termed a hard mask—atop the fin [27]. Now the uppermost surface of the fin will never invert and cannot participate in current flow. The hard-masked device effectively has two gates, both connected electrically, with one controlling each side of the fin.

The BSIM-CMG model includes a SPICE parameter named TMASK . It is used to specify the thickness of the hard mask. Setting TMASK = 0 indicates that there is no hard mask; the dielectric thickness atop the fin then simply defaults to t_ox.[28].

Another aspect of some finFET structures is a fin having a rounded top. This is evident in TEM images of the Intel Ivy Bridge tri-gate transistor. It is likely there to reduce intense fields at the corners—and thus to enhance long-term reliability [4].

In such cases, W_eff is often approximated by 2h_fin. This applies when t_fin < < h_fin. It also applies to double-gate devices , with a hard mask on top of the fin.

2.3.3 Pinched-Off Channel Conditions

From Eq. (2.16), it is clear that the current I_DS begins to level off at higher V_DS values, for fixed V_GS. This gradual leveling off of the I-V characteristic with higher drain bias is known as saturation . As we discussed in Sect. 2.3.2, this happens because the inversion charge layer thins out toward the drain terminal, where the potential drop across the MOS capacitor is lower, by the applied bias V_DS.

At a critical drain bias V_Dsat, the inversion charge Q_i(y) thins out until reaching 0 at the drain end of the fin. The conductive channel is then said to be pinched off.

Let us derive the drain current and drain bias at this critical point of saturation. We evaluate Eq. (2.11) at y = L. Setting Q_i(L) = 0 at pinch-off, and applying the boundary condition V(L) = V_Dsat, we obtain the pinch-off condition below:

$$ {V}_{Dsat}={V}_{GS}-{V}_{Tn} $$

(2.18)

At this drain bias, the channel is pinched off at y = L. The potential drop across the MOS capacitor at that point becomes inadequate to support inversion. But remarkably, drain current will continue to flow, even as the drain bias rises higher.

We can compute this saturation drain current by substituting (2.18) into (2.16):

$$ {I}_{Dsat}={\mu}_n{C}_{ox}\frac{W_{eff}}{2L}{\left({V}_{Dsat}\right)}^2 $$

(2.19)

At pinch-off, we reach the limits of our gradual-channel approximation. The slope of I_DS in (2.16) becomes zero. We conclude from (2.19) that the drain current has reached a saturated value, I_Dsat, and no longer increases with drain bias. Though our GCA model loses validity above V_Dsat, we can explain this current intuitively.

Beyond pinch-off, at drain bias V_DS > V_Dsat, the inversion layer terminates even before y = L. It no longer provides a conductive bridge from the source to the drain.

The voltage at the pinch-off point is still V_Dsat. Beyond it lies a narrow gap, a depleted region, of length ΔL. The voltage drop across this gap is then V_DS − V_Dsat.

The high electric field ∣E_y∣ in the narrow gap sweeps electrons into the drain. For a long-channel device, ΔL < < L. Under these conditions, the inversion channel is not much shorter and still has the same endpoint voltage V_Dsat. To first order, the current flowing through it will remain constant at the saturated value in (2.19).

This physical situation has been likened to a waterfall [29]. As the river runs over the rapids, and the water plummets over the falls, its flow rate is determined not by the height of the falls but by the volume of water flowing through the rapids.

More sophisticated models take into account the shortening of the channel above pinch-off. This leads to the channel-length modulation (CLM) cited in Sect. 2.1. Especially in short-channel devices, the current slowly rises with higher drain bias.

The saturated transistor thus behaves as a constant-current source in shunt with an output resistor. SPICE simulations indicate that the tri-gate finFET has higher output resistance, and thus lower CLM, due to better electrostatic gate control [30].

From Eq. (2.19), we can derive a rule of thumb regarding the drive current of a bulk finFET. Drive is usually expressed as the drain current I_ON flowing when both V_GS and V_DS are biased at the supply voltage VDD. With V_GS tied to V_DS, any transistor with current flowing is always saturated. Thus, (2.19) applies. Ignoring CLM effects, (2.19) tells us that I_ON is determined solely by process parameters.

Rule of Thumb 3

For a nonplanar n-type finFET, similar to a planar MOSFET, the drive current I_ON is proportional to μ_n C_oxW_eff /L. Thus, current drive can be enhanced by scaling down L, increasing W_eff, thinning down oxide thickness t_ox, or enhancing the mobility μ_n.

For tutorial purposes, we have regarded the mobility μ_n as a constant, determined by the silicon lattice. This corresponds to the SPICE parameter U0 . In sophisticated models like BSIM-CMG, this base parameter is adjusted to account for variations in channel length, temperature, and field—even fin characteristics like surface roughness. Mobility is degraded in thin-fin transistors, due to the scattering of charge carriers off the uneven fin sidewalls. Advanced fabrication techniques such as hydrogen annealing smooth the fin sidewalls; this is a practical example of Rule of Thumb 3.

Equation (2.19) also reveals that drive current is affected by the oxide dielectric, primarily through the gate capacitance (per unit area) C_ox. This is a ratio, ε_ox/t_ox.

We can enhance current drive by increasing the numerator, without the need to scale down the denominator. Oxides are already at the limits of scaling—at 4 or 5 molecules thick. Intel introduced the high-κ metal-gate (HKMG) stack, using HfO₂ (or hafnium-based) dielectrics, whose permittivity is ~4× higher than that of SiO₂.

Rule of Thumb 4

The electrical and physical characteristics of finFET devices are enhanced by many of the same process refinements used for planar MOSFETs, including the HKMG gate stack, and mobility improvement by straining the silicon lattice [42, 43].

Now that we have derived the qualitative electrical characteristics of a generic finFET from first principles, let us turn our attention to its geometric characteristics .

2.4 FinFET Layout

Our goal in this section is to consider the layout of a typical CMOS standard cell comprising both n- and p-type finFETs. Many traditional features of planar CMOS geometry carry over to nonplanar finFET technology. In particular, the trend toward highly regular litho-friendly layout, with uniformly pitched polysilicon gate lines, has become even more essential in nanoscale finFET fabrication processes.

The biggest departure from traditional CMOS layout is that transistor width W is no longer a design parameter. Equation (2.17) stated that the effective width W_eff of a one-fin device is fixed by process parameters: fin height h_fin and thickness t_fin.

2.4.1 Fins in Parallel

To adjust the effective width of a finFET , we must resort to laying out multiple fins, in parallel. Figure 2.10 shows a single n-type transistor with three fins. They share a common gate, running across all three fins. These three fins, in shunt, carry a total drain-to-source current I_DS. The effective finFET width has thus been tripled.

Fig. 2.10

An n-type finFET with three fins (perspective view)

Figure 2.10 indicates schematically that the three drain ends are tied together to form a common drain. Similarly, the three source ends are tied together electrically to form a common source. Each fin will thus carry 1/3 of the total current flow I_DS.

Based on this geometry, we can extend Eq. (2.17) for the effective width of a single finFET by including an integer multiplier N_fin (equal to 3 in this figure):

$$ {W}_{eff}={N}_{fin}\left(2{h}_{fin}+{t}_{fin}\right) $$

(2.20)

Integer multiplier N_fin corresponds to the BSIM-CMG SPICE parameter NFIN. In practice it has ranged from 2 to 10. This leads us to a fundamental rule of thumb:

Rule of Thumb 5

The effective width W_eff of a finFET device is quantized. It takes on discrete values, integer multiples of the single-fin width 2h_fin + t_fin. The multiplier is denoted N_fin.

The connections shown schematically in Fig. 2.10 are, in reality, not easy to fabricate. In nanoscale technology, source-drain contact cuts have become so tiny that contact resistance threatens to dominate other parasitic parameters. Each fin in Fig. 2.10 has to carry 1/3 of the total current flow. Significant fin-to-fin variations in contact resistance would render the drive current unpredictable, thus defeating the very purpose of tying fins together in shunt. In the next subsection, we will look at one process-specific solution—a radical departure from classic silicided contacts.

According to (2.20), a straightforward method of enhancing the drive current is to increase the number of fins. Figure 2.11 shows an n-type finFET with five fins. Notice that it still occupies the same silicon area as the transistor of Fig. 2.10. More fins were packed into the same available width. We thus achieved 5/3 the drive current, for the same silicon area. But this increased drive comes at a price.

Fig. 2.11

An n-type finFET with five fins (perspective view)

Layout designers express the dimensions of on-chip geometry using the metric of fin pitch —the center-to-center spacing between adjacent fins. In Fig. 2.10, two fin pitches were required to lay out three adjacent transistors. In Fig. 2.11, four fin pitches were consumed for five transistors—but only by halving the fin pitch.

Half the pitch requires twice the resolution during photolithography. This need has been met by—and in turn fuels the demand for—advanced masking techniques such as self-aligned double patterning (SADP) for critical layers like fins. Double patterning uses two offset masks to pattern a single CMOS layer, instead of one [43].

Rule of Thumb 6

The need for higher finFET drive, achieved by multiple parallel fins, contributes to an industry demand for self-aligned multiple-patterning photolithography methods.

The next subsection explains how the schematic connections in Fig. 2.10 or Fig. 2.11 are fabricated. We will introduce an extra metal layer called METAL0 .

Physical Insight: Litho-Friendly Layout

The bright-colored patterns visible on the underside of an ordinary compact disc are due to light diffracted from the closely spaced 0.5-μm pits that encode the data.

A mask used in photolithography, to print a layer of geometric features onto the wafer, consists of rectangles and polygons spaced even more closely. A feature size of 22 nm is less than the wavelength of the 193-nm UV light transmitted through the mask. This causes the light to diffract (or spread), thus limiting CD resolution.

Resolution enhancement techniques like optical proximity correction (OPC) are necessary to compensate for the distorting effects of neighboring shapes. OPC tools are used, post-layout, to modify the GDSII data describing the geometry on a layer. Just as a small typeface with serifs looks clearer, the altered shapes will print better.

But OPC is computationally intensive, and a single layer can easily run overnight.

Litho-friendly layout is a highly regular design style that alleviates the task of OPC. It avoids any jogs or bends, preferring straight lines and a uniform pitch. Nanoscale finFET technology continues this trend. Fins are laid out in parallel, perpendicular to their poly gate. The gates are also laid out in straight parallel lines. To maximize regularity, dummy poly lines, over STI areas, are drawn at cell edges.

Litho-friendly layout enhances chip manufacturability, at the cost of cell area.

2.4.2 Local Interconnect Layer

Previous figures showed schematically how multiple fins can be tied together to increase the finFET device’s effective width. In the wafer fab, making predictable, low-resistance contacts between individual fins and a metal line is a daunting task.

To solve this issue, fabs like Intel, Samsung, and TSMC have departed radically from classic source-drain contact engineering. At 22 nm, a local interconnect layer was introduced. It uses lines of a refractory metal, like tungsten, running parallel to the gate. Tungsten (W) is ideal for these local connections, because it is able to fill in tiny spaces more easily than copper. It appears as dark gray bars in Fig. 2.12.

Fig. 2.12

A p-type finFET with three fins (side view)

Since this local interconnect layer is below METAL1, it is informally known as METAL0 [43]. It is localized, since it does not extend beyond the ACTIVE area of a single transistor. At a silicon foundry, this layer is fabricated after front-end-of-line (FEOL) base layers but prior to back-end-of-line (BEOL) metallization. It is thus informally referred to as a middle-of-line (MOL) fabrication step.

Let us illustrate the resulting layout using a p-type transistor as our example. Exactly the same layout techniques would apply to a complementary n-type device.

Figure 2.12 is a p-type transistor with three fins. These fins are all implanted PPLUS (except under the poly gate, as shown by the cutaway view). A METAL0 line at left ties together the drain ends. A METAL0 line at the right ties together the source ends. They implement the schematic connections in Figs. 2.10 and 2.11.

The common source must connect to the VDD rail, on the METAL1 layer (not shown). To avoid clutter, an × symbol indicates the site of the square contact cut between METAL1 and METAL0. This contact-cut layer is informally called VIA0.

There is a direct connection everywhere a METAL0 line crosses a fin. One such connection is outlined by the small rectangle. At that point, a trench is etched into the fin. Then an epitaxial silicon apron (not shown) is grown, widening the fin a bit.

The METAL0 line thus solidly contacts the underlying fin on several surfaces. This ensures a predictable, low-resistance connection to each individual fin [4].

From Fig. 2.12, we can infer a key advantage of nonplanar finFET geometry. In this side view, the available width is roughly two fin pitches, or (N_fin − 1)P_fin. This represents the width W that a planar MOSFET would have, if laid out over the same footprint. Using (2.20), we get the ratio below, for a multiple-fin transistor:

$$ \frac{W_{eff}}{W_{MOS}}\approx \frac{N_{fin}\left(2{h}_{fin}+{t}_{fin}\right)}{\left({N}_{fin}-1\right){P}_{fin}} $$

(2.21)

Let us substitute realistic values into (2.21), based on Intel’s second-generation finFET technology, at the 14-nm node. It utilized a fin pitch and a fin height both equal to 42 nm. The fin width was 8 nm [31, 43]. The ratio that results from (2.21), for a three-fin transistor, is over 3. This leads to the rough rule of thumb below:

Rule of Thumb 7

Nonplanar finFET devices can pack ~3× the transistor width into the same area as planar devices—since their effective width W_eff extends partly in the z-direction. This implies high drive, without any impact on circuit area—a critical advantage in such applications as high-density SRAM memory arrays designed using finFETs.

According to (2.21), this advantage hinges on a tight fin pitch P_fin and a tall fin of height h_fin. Fabricating very tall fins, of course, poses difficulties in processing. Fins taller than 4t_fin may risk instability unless more area is allowed at the base [32].

We have investigated the geometry of a single finFET with multiple fins. Now let us extend these principles to the detailed layout of a typical CMOS standard cell.

2.4.3 Standard-Cell Layout

Figure 2.13 shows a generic standard-cell layout of a finFET NAND2 gate. This layout is litho-friendly, arranged along regularly spaced horizontal and vertical lines. The two vertical poly lines are driven by the gate’s inputs A and B. Running parallel to these lines are the local interconnects, on METAL0, which tie together the source or drain ends of the fins. (To improve clarity, no dummy poly lines are shown. Neither is the required n-type well that must enclose the p-type transistors.)

Fig. 2.13

NAND2 standard cell (layout view)

Recall that each METAL0 segment directly connects to the fins that it overlaps. Each such segment thus defines a common source or drain. In turn, the METAL0 segment connects to the next metal layer, METAL1, through at least one VIA0 cut.

An active area defines a rectangular region for transistors of the same type. Outside an active rectangle is STI oxide. The lower active area in Fig. 2.13 has two n-type transistors in series, the pull-down network of this NAND2. Output Y is thus pulled down to ground if both gate inputs A and B are at a logic-high value.

The upper active area has two p-type transistors in shunt—the pull-up network. Output Y is pulled up to the VDD rail if either or both inputs are at a logic-low value. The resulting gate output is thus Y = ~(A·B).

Notice that the p-type transistors in the pull-up network are laid out with five fins, while the n-type devices in the pull-down network have three fins. Transistors are sized in this way to balance rising and falling NAND2 output delays. Increasing the width of p-type devices compensates for the lower mobility of holes—equalizing speed.

Mobility engineering in finFETs, however, is a topic of intensive research. Such process enhancements as fin crystal orientation promise simultaneous optimization of μ_n and μ_p without the need for the designer to widen every p-type transistor [33].

We can conclude from Fig. 2.13 that laying out a standard cell using finFETs is a more complex design task than for planar MOSFETs. Laying out an analog macro can take 4× the effort, although the performance is well worth the effort [34].

Automated layout tools can facilitate the task. With Synopsys Custom Designer , for example, the user can draw a finFET transistor to the same width W as its planar counterpart—and the tool will split it into multiple fins, at design-rule spacing [35].

Referring to this standard cell, we can infer several geometric rules of thumb:

Rule of Thumb 8

An exposed fin, crossing an ACTIVE area, and surrounded by NPLUS (or PPLUS), becomes the source or drain of a transistor. If overlapped by POLY, it is a channel.

Rule of Thumb 9

A METAL0 line crossing fins within an ACTIVE area directly ties them together, at the local interconnect level, forming the common source or drain of a transistor.

Rule of Thumb 10

The output of a typical (static) CMOS standard cell is a metal segment that connects a source or drain that is inside the NPLUS mask, with one inside the PPLUS mask.

In the previous sections, we introduced nonplanar transistors like the SNWFET and the finFET. We derived their electrical characteristics to first order, using GCA assumptions. Along the way, we listed practical rules of thumb—some of which reflected qualitative similarities between planar and nonplanar field-effect devices.

The next section explores the key difference: a nonplanar transistor of length L is inherently more immune to SCEs than a traditional planar device of equal length.

2.5 Short-Channel FinFETs

We saw in Fig. 2.1 that a short-channel MOSFET is no longer very planar. The gate fully controls only a fraction of the channel length L. It loses control over the areas near the source and drain—indicated in that figure by two shaded triangles.

This encroachment arises from the depletion region around the source and drain. At its maximum depth, the total depletion charge is −qN_AWLd_max. But the shaded fraction of depletion charge in Fig. 2.1 needs no gate voltage to build up. It is a by-product of the p-n junctions between the source or drain and the substrate. The channel inverts at a lower gate voltage, and V_Tn rolls off with shorter length L. With further scaling, the relative fraction of shaded charge grows. Roll-off gets worse.

This roll-off can also be inferred from Eq. (2.6). This expression for V_Tn, derived under gradual-channel conditions, includes a total depletion charge |Q_d| induced by the gate bias. For shorter channels, a fraction of this charge is built into the source-drain p-n junctions and needs no gate voltage. Thus, V_Tn becomes lower.

In striking contrast to the traditional planar short-channel MOSFET, nonplanar devices like the SNWFET in Figs. 2.2 and 2.3, and the finFET in Fig. 2.6, are far more symmetric. Their gate electrodes wrap around the conducting channel—all the way, for a nanowire device, or three-fourths of the way, for a tri-gate finFET.

This wraparound effect maximizes the electrostatic control of gate over channel. This explains qualitatively why the finFET device would show higher immunity to the SCEs cited in Sect. 2.1. But is there a more quantitative explanation? Can we find a rule of thumb to estimate the channel length L below which SCEs will set in?

2.5.1 Natural Screening Length

The answer to these questions lies in the detailed solution of Poisson’s equation. We visited this equation in (2.1), for a cylindrically symmetric SNWFET. A similar equation, using rectangular coordinates, applies to the less-symmetric finFET. Its analytical solution is even more complex and well beyond the scope of a tutorial.

Poisson’s equation can, however, be transformed into the simpler form (2.22), where λ is a process-dependent length parameter and φ(y) is the transformed potential (with an added fixed-charge term) along the channel [36,37,38]:

$$ \frac{d^2\varphi }{dy^2}=\frac{1}{\lambda^2}\varphi (y) $$

(2.22)

This transformed differential equation, along with its boundary conditions at the source and drain, has a solution made up of exponential terms of form exp±(y/λ). Parameter λ is interpreted as a natural screening length, with values as in Table 2.1.

Table 2.1 Natural screening length λ for field-effect devices [39, 40]

Physically, λ is a characteristic length representing the degree of encroachment of source-drain field lines into the channel (like the shaded triangles in Fig. 2.1). It depends on device geometry and process parameters. If λ is a large fraction of L, then the influence of source or drain over the channel will fall away slowly, due to exp − (y/λ) or exp − [(L − y)/λ] terms. Such a device exhibits pronounced SCEs.

But if λ is a small fraction of L, then the undesired influence of the source or drain over channel conditions falls away more quickly. Beyond a few λ, the field lines from source or drain become negligible. Such a device will be free of SCEs.

Though λ is highly dependent on process-specific parameters, the sample values in Table 2.1 suggest that the tri-gate finFET has a smaller λ than a planar MOSFET. This explains quantitatively its inherently higher immunity to short-channel effects. (The SNWFET, especially at smaller diameter t_nw, is potentially the most immune.)

Rule of Thumb 11

To shorten the screening length λ for the tri-gate finFET, thus suppressing SCEs, reduce the fin thickness t_fin or increase the gate capacitance C_ox  = ε_ox/t_ox.

For a tri-gate finFET device, Table 2.1 shows that λ depends only on the product t_fin t_ox. This allows trade-offs. We can scale down either fin thickness or gate oxide. Notice another advantage of the finFET. There is no need to increase the channel doping, just to reduce depletion-layer width d_max, as in traditional planar devices. Lightly doped fins enhance mobility, since carriers are not scattered as frequently.

Based on the exponential form of solutions to (2.22), and recalling that exp(−3) is 5%, we can state a rough rule of thumb that applies to any device in Table 2.1:

Rule of Thumb 12

To avoid SCEs, a field-effect device should have at least a channel length L > 3λ .

Referring to the sample values of λ in Table 2.1, row b, we can conclude that a tri-gate finFET device of channel length 14 nm (or 3.5λ) is relatively free of SCEs. But a planar MOSFET of the same length (0.6λ, from row a) has pronounced SCEs.

Physical Insight: Natural Screening Length

Mathematically, a parameter like 1/λ² in (2.22) is known as an eigenvalue of the differential equation. Derivative d²φ(y)/dy² returns the original function, scaled by a factor 1/λ² whose value is fixed by boundary conditions. This invariance under transformation holds only for specific, physically meaningful values. Schrödinger’s equation for an electron inside a potential well, for example, results in quantized energy eigenvalues which define the allowed stationary states of the electron.

Screening length λ seems to be a physically meaningful parameter for nonplanar transistors. This has been demonstrated by numerical simulations of short-channel effects (such as DIBL) versus device length L . When such simulations are run on a wide variety of double-gate, tri-gate, and similar nonplanar devices—and plotted against the normalized variable L/λ—they all fall on the same common curve [41].

2.5.2 BSIM-CMG SPICE Model

During the preceding sections, we considered several members of the family of nonplanar transistors. Though the geometry of a nanowire device appears radically different from that of a bulk tri-gate or double-gate device, they in fact share many common properties. In this subsection, we take a brief look at an industry-standard model, BSIM-CMG, which can simulate any of these family members using SPICE.

The output plots or data from BSIM-CMG simulations accurately model all of the short-channel effects and quantum-mechanical effects exhibited by these devices.

This turnkey common multiple-gate model applies to double-gate, triple-gate, or wraparound-gate devices—whose gates all form part of the same electrical node and share a common bias V_GS. (Devices like a double-gate finFET in which separate bias voltages can be applied independently to the two gate halves must use another model, BSIM-IMG. In this tutorial, we have considered only common-gate devices.)

These are complex models. To run a SPICE simulation using BSIM-CMG, users must specify—or accept defaults for—over 200 parameters describing the device and process. Foundries routinely provide this data to their customer base, in the form of n-type and p-type .MODEL files that can be included in a SPICE deck. We will highlight just a few global parameters which determine the type of device.

The BULKMOD parameter selects the kind of wafer on which the finFET devices are fabricated. It has two values: 0 for SOI substrates and 1 for bulk silicon substrates. The GEOMOD parameter selects the geometry model. The values relevant to this tutorial are 0 for double-gate finFET, 1 for tri-gate, and 3 for cylindrical SNWFET.

The bulk p-type five-fin transistor used in the NAND2 of Fig. 2.13 would thus be modeled by a SPICE card with many parameters. The first lines might resemble:

.MODEL pFET pMOS LEVEL=72 + BULKMOD=1 GEOMOD=1 NFIN=1 EPSRSUB=12 U0=0.03 … .

where the default fin number is overridden when the transistor is instantiated by specifying NFIN = 5. Notice NFIN now replaces the traditional MOSFET width W. The BSIM-CMG model is written in Verilog-A. Developed at UC Berkeley, it can be downloaded at no cost, with a technical manual describing all its parameters [28].

2.5.3 Strengths and Weaknesses

In this closing subsection, we summarize a few of the strengths and weaknesses of the generic bulk n-type finFET in Fig. 2.6 (or its p-type counterpart). Based on published data from Intel, this nonplanar 22-nm tri-gate transistor is in high-volume production [42]. It has a higher I_ON and lower I_OFF current than did its planar 32-nm predecessor. The higher I_ON/I_OFF ratio demonstrates improved immunity to SCEs.

In addition, finFET technology has proven versatile, with options for low-power, high-speed, I/O-voltage , and on-chip analog/RF devices. Its first-generation success has led Intel to develop a second-generation finFET with a more rectangular fin [43].

Several of the representative strengths of finFET devices are summarized below:

• Enhanced scalability : Due to improved electrostatic control of the gate over the channel—as indicated by smaller values of screening length λ—the finFET is less prone to SCEs such as threshold roll-off and subthreshold conduction. This enhanced scalability potentially extends Moore’s law for years to come.

• Lower I_OFF current : Below threshold, the finFET is turned off more fully than a planar MOSFET of similar dimensions. This reduces standby leakage power. The figure of merit typically employed is low subthreshold swing, measured in mV/decade of leakage current. Intel’s 22-nm low-power finFET devices showed a swing of only 65 mV/decade, compared to 100 for planar 32-nm devices [42].

• Higher I_ON drive in same-cell area: Standard cells using finFET transistors can pack several times the device width into the same cell footprint as planar standard cells—because the effective width W_eff of nonplanar devices extends partly upward from the substrate. This requires tight fin pitch but yields higher drive current, with no corresponding penalty in standard-cell or SRAM-cell area.

• Enhanced mobility : The finFET has proven to be compatible with the various strain-engineering techniques used to enhance mobility in planar MOS devices. Its vertical fin may enable still other refinements. While the face of the standard silicon wafer lies in the (100) crystal plane, individual fins could be oriented along other axes, characterized by higher hole mobility μ_p (or by equal μ_n and μ_p). Such process refinements might reduce the need to widen p-type devices.

• LP, HP, I/O device types: The finFET transistor has qualified as a platform SOC technology . It can support a mixed family of devices on one die, including low-power, high-performance, higher (I/O) voltage, SRAM, and analog/RF. As one example, Intel’s 22-nm process employed longer (40-nm) finFETs for either ultra-low-power logic with a very low subthreshold current or higher-voltage devices to handle legacy 1.8 or 3.3 V I/Os, voltage regulators, or transceivers [42]. Several representative strengths of the finFET device are summarized below:

• Quantized width : The effective finFET transistor width W_eff is quantized and can be adjusted higher only by laying out more fins connected in shunt. This complicates layout. Precise device sizing is harder, making it difficult to trade off performance and power. A tight fin pitch is essential for fine-grained width adjustment. This is especially true for sizing and floor planning analog blocks, since device widths are quantized, and the fins must be laid out in parallel lines.

• Overheating in fin: Localized overheating can result from high-drive currents flowing through thin fins. The heating can degrade I_ON. In the long term, it may be a reliability problem. Less of an issue for bulk finFETs, whose fins are thermally coupled to the substrate, it may be more of an issue for silicon-on-insulator (SOI) finFETs, fabricated upon a buried-oxide layer. The thermal conductivity of a thin layer of SiO₂ can be two orders of magnitude lower than for bulk silicon.

• Parasitic capacitance : Parasitic values are process-specific. Because the fin is a vertical ridge, finFETs tend to have less parasitic junction capacitance C_j than planar MOSFETs, with their wide, flat source and drain areas. But a tall fin and gate stack, in close proximity to local interconnect lines, can result in higher gate-to-source/drain parasitic capacitance C_gs between the gate and the exposed fins or METAL0 lines forming the common source and drain. In general, the 3-D structure of a finFET complicates the extraction of parasitic RC values from device geometry. There are more parasitic elements to compute, per transistor.

• Parasitic resistance: High parasitic resistance can arise from the source and drain terminals at both ends of the thin fin, compared to the planar MOSFET. This was evident in Fig. 2.7. High series R can impact on-chip RF circuits via lower transconductance g_m, which affects amplifier gain or frequency response.

Though accurate long-term predictions are not easy to make in the fast-changing semiconductor industry, the nonplanar finFET device, with its almost wraparound gate terminal and its maximal electrostatic control over the channel, promises to extend Moore’s law, avoiding short-channel effects, to at least the 3-nm node [44].

Glossary

Analog/RF CMOS

As used in this tutorial, it refers to analog circuits (from low- to radio-frequency and even millimeter wave) on a mostly digital CMOS chip. This presents a challenge for the analog designer, since any CMOS fabrication process is optimized for noisy digital logic, not sensitive analog functions such as low-noise amplifiers or wireless transceivers. Digital processes offer simple speed vs. power trade-offs, while analog circuits may need optimizing for gain, linearity, or noise.

BSIM SPICE models

The acronym stands for Berkeley short-channel IGFET (insulated gate) model. Older versions, like BSIM3 and BSIM4, model traditional MOSFETs, up to the 22-nm node. Newer versions like BSIM-CMG model nonplanar devices like the finFET. These models stem from the principles of device physics (like the GCA equations used in this tutorial), rather than purely empirical formulas.

Carrier concentration

In contrast to metallic conductors such as aluminum or copper, semiconductors have two independent charge carriers: electrons and holes. The behavior of diodes, transistors, and other semiconductor devices often hinges upon the relative concentrations of holes (p) and electrons (n), expressed in carriers per cm³. In pure silicon, they are thermally generated in pairs. In this intrinsic state, n and p remain equal. Their product is np = n_i² ≈ 10¹⁰ cm⁻³ at room temperature.

In a p-type substrate, however, the substitution of acceptor atoms (like boron) into the silicon lattice results in an excess of holes. Then p_p > > n_p, indicating an excess of majority-carrier holes over minority-carrier electrons. The product np = n_i² will remain constant under thermal equilibrium (no applied bias or other perturbations).

CD

An acronym familiar to fab engineers, denoting any critical dimension of a feature on a wafer. CDs can be measured in the fab by a CD-SEM. For example, an Intel engineer might plot subthreshold swing as a function of the measured width of a poly line crossing a fin, in nm. This CD is a routine measure of channel length L.

Drain-induced barrier lowering (DIBL)

When the drain bias of a short-channel device increases from low to saturated values, threshold roll-off is aggravated. (The shaded triangles in Fig. 2.1 indicated how roll-off occurs at low drain bias. DIBL occurs at higher V_DS values.) The drain bias affects the potential distribution, lowering barriers to subthreshold conduction. This SCE is measured in mV per volt.

Inversion

In an n-type MOS transistor at the onset of inversion, the concentration of minority electrons flooding into the channel just equals that of holes deep within the p-type substrate. Thus, n_p(0) = p_p(∞), where coordinate 0 refers to the silicon surface. The relative concentration of minority and majority carriers thus becomes inverted. Above this threshold, n_p(0) rises exponentially with surface potential Φ_s.

Permittivity ε₀

Intuitively, the electrical permittivity ε₀ of free space is equal to the capacitance of a cube-shaped parallel-plate capacitor, filled with a vacuum, of 1 cm thickness and 1 cm² area. A fundamental constant, it equals 8.85 × 10⁻¹⁴ F/cm.

PTM SPICE models

The acronym is for predictive technology model , which evolved from predictive modeling efforts at Berkeley, and is now advanced by the Nanoscale Integration and Modeling Group at the Arizona State University. A goal of this group is predictive modeling, applicable to the next generation of technology—not only finFET devices down to 7 nm but even to future carbon nanotube devices.

Silicon on insulator (SOI)

A promising alternative to bulk finFET technology, in which transistors are fabricated directly on a silicon wafer. In SOI technology, an insulating oxide layer (the buried oxide, or BOX) is implanted below the surface of the entire wafer. FinFET transistors are fabricated into the thin layer of silicon left on top. Due to the BOX, there is little or no parasitic capacitance to the substrate. Another advantage of SOI wafers is that no well is needed around p-type devices. The trade-off is a higher SOI base wafer cost—as much as 4× higher than bulk.

Subthreshold swing (SS)

Subthreshold current is one of the worst SCEs. It makes a short-channel transistor too leaky to turn completely off. Since this current falls off exponentially as V_GS drops below V_T, it is ordinarily plotted on a log scale. The slope of this log-linear plot is then ∂log(I_DS)/∂V_GS. In the lab, it is more convenient to measure the reciprocal of this slope, in mV per decade of current, often called subthreshold swing. It has a theoretical minimum of 60 mV/decade—which Intel nearly met with its 22-nm finFET. Devices which swing higher are more leaky.

Verilog-A

An addition to the Verilog digital hardware description language was able to model analog circuits as well. It includes an analog code block, as well as the usual always. Since BSIM-CMG is written in Verilog-A, it can use classic case syntax, like case(GEOMOD), to check a parameter and set values accordingly. It can also use analog operators like ddt(q) to differentiate charge, yielding current.