- Elmsford, New York, United States
Research Interests: Materials Engineering, Physics, Condensed Matter Physics, Superconductors, Radio Frequency, and 11 moreField Programmable Gate Array, Chip, Room Temperature, Demodulation, Decimation, Superconductor, Phase Modulation, Wideband, Electrical And Electronic Engineering, Commercial Off-The-Shelf, and Analog to Digital Converter
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As digital superconductor circuits based on Rapid Single Flux Quantum (RSFQ) logic scale up in complexity, so does the total current required to provide dc bias. Serial biasing (SB) is a promising solution that can be used to reduce the... more
As digital superconductor circuits based on Rapid Single Flux Quantum (RSFQ) logic scale up in complexity, so does the total current required to provide dc bias. Serial biasing (SB) is a promising solution that can be used to reduce the current by placing identical digital blocks on islands with isolated grounds and bias them sequentially. There are typically two implementations that are essential for the SB approach: the design of a driver-receiver pair (DRP) for inter-island pulse transport and the current management technique to handle the bias current flowing into and out of an island. While a DRP with good fidelity is essential for any serially biased circuit, the current management becomes critical for designs with relatively large bias current. In this paper, we address the latter. First, we propose a grapevine biasing scheme for serial bias current management. Second, we implement the technique using two exemplar circuits: the parallel counter and the digital decimation filter. We report the low and high speed test results up to 50 GHz for both circuits fabricated at MIT-LL in the SFQ5ee 10 kA/2 Ω fab node.
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Cryocooled wideband digital channelizing radio-frequency receiver based on low-pass ADC
Fast time-to-digital converters (TDCs), used to convert a continuous time interval into discrete number for further processing, serve diverse applications ranging from photon/particle detectors to communication systems employing... more
Fast time-to-digital converters (TDCs), used to convert a continuous time interval into discrete number for further processing, serve diverse applications ranging from photon/particle detectors to communication systems employing delay-encoded pulses. Being a multi-rate digital circuit, the TDC is also a good candidate to explore operation of Energy-Efficient Rapid Single Flux Quantum (ERSFQ) circuits at high (>10 GHz) clock frequency. We designed a TDC using ERSFQ cells, targeting the 10-kA/cm2 SFQ5ee fabrication process at MIT Lincoln Laboratory. The main elements of the circuit comprise a 9-bit binary ripple counter and a parallel-to-serial converter. A frequency divider and a pulse distribution network with a decision-making element are designed to control the operation. The ERSFQ TDC was operated up to 25 GHz clock frequency (40 ps time resolution) and with a power consumption of around 14 µW for all ERSFQ components. The design specifications such as number of junctions and ...
Passive transmission lines (PTLs) provide an energy-efficient means of transporting pulsed single flux quantum (SFQ) signals between logic gates and blocks on a chip, or even between chips through a multi-chip module carrier. Although... more
Passive transmission lines (PTLs) provide an energy-efficient means of transporting pulsed single flux quantum (SFQ) signals between logic gates and blocks on a chip, or even between chips through a multi-chip module carrier. Although functional up to 70 GHz, our previous designs manifested sharp, length-dependent resonances resulting in diminished operating margins. These are particularly inconvenient since the resonant length is about 1 mm at 40–50 GHz, where most SFQ circuits currently function. To avoid the need to keep the PTLs < 1 mm in length, we have optimized the PTL driver-receiver pairs to sufficiently suppress these resonances; this helps facilitate the use of automated routing tools. We present experimental results, in the 10-70 GHz frequency range, for different driver-receiver pairs designed for PTLs in our dual RSFQ-ERSFQ cell library. This cell library, targeting MIT Lincoln Laboratory's SFQ5ee fabrication process, uses PTLs with two types of ground plane configuration. The first variant has signal in M1 and/or M3 with symmetrical ground planes in M0, M2 and/or M2, M4 respectively. The second variant has signal in M2 and/or M3 with asymmetrical ground planes in M1 and M4. We also present a comparison with wider, 4 Ω, PTLs that are more suitable for transport between distant logic blocks. Next, we present experimental results of PTL lengths ranging from 1.2-12 mm over the same 10-70 GHz frequency range. Finally, we report on the design of circuits for investigating crosstalk between two PTLs and their measurement results.
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The Josephson balanced comparator is the key component of Single Flux Quantum logic devices because it is the decision making element. It is formed by two Josephson junctions (JJs) connected in series from a clocking perspective and in... more
The Josephson balanced comparator is the key component of Single Flux Quantum logic devices because it is the decision making element. It is formed by two Josephson junctions (JJs) connected in series from a clocking perspective and in parallel for the current to be measured. Its noise properties are crucial for the performance of logic devices. The balanced comparator can also be used to monitor the fab process and design implementation as an indicator of excess noise, overheating, linearity, dynamic effects, etc. We designed several test structures to measure the comparator gray zone at different fabrication process nodes at MIT-LL. We used digital circuitry to measure comparator characteristics at low frequencies. An analog testbed was used to perform high-frequency characterization. Experimental results for different current densities, sheet resistances, damping and clock frequencies are presented.
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Historically one of the most challenging high-speed rapid single flux quantum circuits to implement has been a parallel counter that sums a set of unweighted inputs and produces a binary-weighted word at the same clock rate. A 7-to-3... more
Historically one of the most challenging high-speed rapid single flux quantum circuits to implement has been a parallel counter that sums a set of unweighted inputs and produces a binary-weighted word at the same clock rate. A 7-to-3 parallel counter that sums seven inputs has been designed and tested at the target clock frequency of 40 GHz and at frequencies up to 50 GHz using its own dedicated testbed. Yielded in both 10- and 20-kA/cm2 current densities using MIT Lincoln Laboratory's foundry, this 7-to-3 summing circuit has become a digital circuit benchmark. Most recently, a version with 15 parallel inputs producing a 4-bit output at the same target frequency was designed by combining 2 variants of 8-to-4 parallel counters. The first variant based on the 7-to-3 parallel counter, sums eight unweighted inputs, whereas the second variant sums two 4-bit binary-weighted words by pairwise summing of bits of equal weights. Design considerations for scaling this circuit will be discussed together with the circuit performance and yield.
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The signal-to-noise ratio (SNR) of a low-pass phase modulation–demodulation analog-to-digital converter (LP PMD ADC) depends on the number of channels in its demodulator (synchronizer or race arbiter). For 3, 7, and 15 channels, this... more
The signal-to-noise ratio (SNR) of a low-pass phase modulation–demodulation analog-to-digital converter (LP PMD ADC) depends on the number of channels in its demodulator (synchronizer or race arbiter). For 3, 7, and 15 channels, this gives 9.5, 16.9, and 23.5 dB theoretical SNR gain in comparison to a single channel. We have designed a family of parallel counters that sums the unweighted outputs of each synchronizer channel to produce a binary code. A 7-to-3 counter that can be truncated into 3-to-2 and extended into 15-to-4 adders was fabricated using 10 and 20 kA/cm2 MIT-LL processes and successfully tested. The completed designs of 1-, 3-, and 7-channel LP PMD ADC are also briefly discussed.
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We designed and tested the digital readout circuitry for superconducting nanowire single-photon detectors (SNSPDs). The designed time-to-digital converter (TDC) comprises a decision-making block, a clock controller, and a counter with... more
We designed and tested the digital readout circuitry for superconducting nanowire single-photon detectors (SNSPDs). The designed time-to-digital converter (TDC) comprises a decision-making block, a clock controller, and a counter with parallel-to-serial (P2S) interface. We also designed an on-chip pattern generator to imitate a digitized SNSPD response that allowed us to screen the circuitry without bonding actual SNSPDs. Both rapid single-flux quantum (RSFQ) and its energy-efficient rapid single-flux quantum (ERSFQ) versions were designed for comparison and debugging purposes. To optimize the design of the feeding Josephson transmission line (FJTL) required by the ERSFQ variant, we compared different power grid structures and types of FJTLs. Using an 8-bit counter with P2S interface as a device under test, we also investigated the effect of FJTL's size on the bias margins. FJTL with a 75% junction overhead is sufficient for the ERSFQ circuit to match the margins of its RSFQ counterpart. All chips have been fabricated at MIT-LL using the SFQ5ee process node. Experimental results and future research directions are presented.
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As the complexity of superconductor circuits grows, we envision a dense network of passive transmission lines (PTLs) being used to interconnect cells in rapid-single-flux-quantum (RSFQ) circuits. In our library approach, each cell has... more
As the complexity of superconductor circuits grows, we envision a dense network of passive transmission lines (PTLs) being used to interconnect cells in rapid-single-flux-quantum (RSFQ) circuits. In our library approach, each cell has dedicated tracks as place holders for routing PTLs. Higher impedance PTLs are desirable due to their narrower width. However, at higher impedance, the margins for the PTL receiver degrade rapidly. We have designed, fabricated, tested, and simulated passive transmission lines (PTLs) for high-speed interconnects in the MIT-LL SFQ5ee 10 kA/cm2 process. For the symmetric dual ground planes case, PTLs are in the M1 layer with M0 and M2 ground planes, or in the M3 layer with M2 and M4 ground planes. For the asymmetrical dual ground planes case, PTLs are in M2 or M3 layers with M1 and M4 ground planes. We report ±30% margins for these PTLs. We investigate the receiver margins for these PTLs and report impact of margins as a function of corners, interlayer transitions, variants of drivers, and receivers. We demonstrate 100 GHz PTL operation in ring oscillator measurements. We have also adopted multi-layer multi-conductor transmission line models for PTL simulation. We observe good model-to-hardware correlation for low- and high-frequency operation.
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As the digital data links for superconducting circuits advance and higher data throughput per channel becomes possible, timing margins shrink and data integrity becomes a major challenge. Particular interest for multichannel applications... more
As the digital data links for superconducting circuits advance and higher data throughput per channel becomes possible, timing margins shrink and data integrity becomes a major challenge. Particular interest for multichannel applications is establishing the high-quality data link to interface with subsequent electronics. In this paper, we focus on integration of an on-chip pseudorandom binary sequence (PRBS) generator into a superconducting analog-to-digital converter (ADC) design to facilitate link stability evaluation and automated interchannel synchronization. PRBS generator and the ADC use a common clock source. An on-chip deserializer/demux, which includes the output drivers, is driven by a set of data sources depending on switch selections on-chip. The outputs are connected to a field-programmable gate array (FPGA) at room temperature, which hosts the developed interface circuitry for data reception, data integrity evaluation, and the synchronization mechanism. The integrated circuit (IC) that combines ADC and PRBS7 generator circuit was designed for the HYPRES 4.5 kA/cm2 four-layer standard fabrication process and features four deserialized outputs. A second similar IC was designed comprising an ADC frontend as well as a PRBS15 generator and was fabricated in the MIT-LL 10 kA/cm2 process. The implemented alignment engine that bonds the individual channels into a single data link was proven up to 10 Gbps while taking 1–2 μs to complete the alignment. We built chip-to-FPGA data links, comprising the on-chip driver and room-temperature interface amplifier, up to 14 Gbps using FPGA serial-link GTY transceiver. Successful data transport from an ADC using multiple parallel data links to an FPGA upon completion of the channel bonding was demonstrated.
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One of the crucial factors in achieving high performance of superconducting integrated circuits, such as analog-to-digital converters (ADCs), is sampling using a high-frequency clock source with a low cycle-to-cycle jitter. As the... more
One of the crucial factors in achieving high performance of superconducting integrated circuits, such as analog-to-digital converters (ADCs), is sampling using a high-frequency clock source with a low cycle-to-cycle jitter. As the superconductor ADC technology matures toward more complex designs for higher dynamic range performance, the need for synchronous clocking of multiple comparators continues to grow. Since high-frequency external clock sources are expensive and make a significant contribution to the heat load of the system, a high-frequency and low-jitter on-chip clock source using long Josephson junction (LJJ) is considered the preferred long-term solution. Toward that end, we are working on improving an on-chip 110-GHz clock source based on an unshunted LJJ in annular geometry. Minimizing the additional jitter added by each fan-out of the clock signal is the effort's goal. For synchronous clocking of up to three comparators, we compare clock distribution using superconducting passive transmission lines and a new approach using novel active transmission lines. We also introduce a method of synchronizing LJJ clock source with an external stable oscillator by injection locking.
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ABSTRACT A superconducting digital-RF receiver with high-ingest-rate data recording capability has been developed. The data recorder unit uses standard PC components with state-of-the-art solid-state drives (SSDs) and interfaces with the... more
ABSTRACT A superconducting digital-RF receiver with high-ingest-rate data recording capability has been developed. The data recorder unit uses standard PC components with state-of-the-art solid-state drives (SSDs) and interfaces with the superconductor analog-to-digital converter (ADC) through a commercial FPGA board. High-speed data ingest rates exceeding 3.2 Gbps have been demonstrated successfully with single-bit ADCs clocked up to 27.52 GHz. A continuous recording of 2.5 TB has been achieved using a bank of 12 SSDs. A new graphical user interface featuring single button operation and automatic file naming, as well as convenient configuration setting, has been developed.
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ABSTRACT A superconducting digital-RF receiver with high ingest-rate data recording capability has been developed. The data recorder unit uses standard PC components with state-of-the-art solid-state drives and interfaces with the... more
ABSTRACT A superconducting digital-RF receiver with high ingest-rate data recording capability has been developed. The data recorder unit uses standard PC components with state-of-the-art solid-state drives and interfaces with the superconductor analog-to-digital converter (ADC) through a commercial FPGA board. High-speed data ingest rates exceeding 3.2 GBps have been demonstrated successfully with single-bit ADCs clocked up to 27.52 GHz. Long data acquisitions are useful for analyzing ADC performance in terms of stability and linearity. A data analysis program has also been developed to extract performance parameters and visualize digitized signals in frequency and time domains.
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The Josephson balanced comparator, a decision-making circuit comprising two Josephson junctions (JJs) connected in series from a clocking perspective and in parallel for the current to be measured, is ubiquitous in single flux quantum... more
The Josephson balanced comparator, a decision-making circuit comprising two Josephson junctions (JJs) connected in series from a clocking perspective and in parallel for the current to be measured, is ubiquitous in single flux quantum (SFQ) logic. Its noise properties are crucial for the performance of logic devices. The characteristics of the balanced comparator can also be used to monitor fab process and design implementation as an indicator for excess noise, overheating, linearity, dynamic effects, etc. We designed several test structures to measure gray zone of various comparators fabricated in different nodes of process at MIT-LL. We used digital circuitry to measure comparator characteristics at low frequencies and an analog testbed to perform high frequency characterization. Experimental results for gray zone of comparators designed for fabrication nodes with different current densities, sheet resistances, critical damping are presented and studied as a function of clock frequency.
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Abstract We describe the design of a new demodulator for continuous phase frequency modulated signals such as link-16 messages. A link-16 message consists of short RF pulses containing 32 ldquochipsrdquo each one having duration of 200... more
Abstract We describe the design of a new demodulator for continuous phase frequency modulated signals such as link-16 messages. A link-16 message consists of short RF pulses containing 32 ldquochipsrdquo each one having duration of 200 ns. One of the main ...
Research Interests: Materials Engineering, Condensed Matter Physics, Comparative Study, Field Programmable Gate Array, Implementation, and 10 moreExperimental Evaluation, Chip, Modulator, Room Temperature, Demodulation, Digital Filter Design, Digital Filters, Analog to Digital Conversion, Electrical And Electronic Engineering, and Low Pass Filters
Abstract We describe the design of a new demodulator for continuous phase frequency modulated signals such as link-16 messages. A link-16 message consists of short RF pulses containing 32 ldquochipsrdquo each one having duration of 200... more
Abstract We describe the design of a new demodulator for continuous phase frequency modulated signals such as link-16 messages. A link-16 message consists of short RF pulses containing 32 ldquochipsrdquo each one having duration of 200 ns. One of the main ...
Research Interests: Materials Engineering, Condensed Matter Physics, Comparative Study, Field Programmable Gate Array, Implementation, and 10 moreExperimental Evaluation, Chip, Modulator, Room Temperature, Demodulation, Digital Filter Design, Digital Filters, Analog to Digital Conversion, Electrical And Electronic Engineering, and Low Pass Filters
Abstract A custom-designed laboratory prototype of a four-stage Stirling-type pulse tube cryocooler was recently developed by Lockheed Martin for niobium integrated circuits (ICs) operating close to 4 K. Basic system performance has been... more
Abstract A custom-designed laboratory prototype of a four-stage Stirling-type pulse tube cryocooler was recently developed by Lockheed Martin for niobium integrated circuits (ICs) operating close to 4 K. Basic system performance has been verified by integration with a ...
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Abstract An advanced version of a two stage dc SQUID-based low frequency amplifier and its measured signal and noise parameters are presented in this report. An effective input inductance of about 2.9 μH, a SQUID&#x27;s inductance of... more
Abstract An advanced version of a two stage dc SQUID-based low frequency amplifier and its measured signal and noise parameters are presented in this report. An effective input inductance of about 2.9 μH, a SQUID&#x27;s inductance of about 11 pH, an effective coupling k ...
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ABSTRACT A description is given of the design, fabrication technology, and characteristics of a sensor for a scanning magnetic microscope using a thin-film dc SQUID with Nb/Al2O3/Nb shunted Josephson tunnel junctions. It is shown that at... more
ABSTRACT A description is given of the design, fabrication technology, and characteristics of a sensor for a scanning magnetic microscope using a thin-film dc SQUID with Nb/Al2O3/Nb shunted Josephson tunnel junctions. It is shown that at a sample temperature of 4.2 K the spatial resolution of this detector is 10 µm with a field resolution of 70 pT/Hz1/2.
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The integrated version of a two stage dc SQUID-based low frequency amplifier has been designed, fabricated and tested. The value of the gain of the applied flux d/spl Phi//sub SQ2//d/spl Phi//sub SQ1/ in the range 30-70 and an overall... more
The integrated version of a two stage dc SQUID-based low frequency amplifier has been designed, fabricated and tested. The value of the gain of the applied flux d/spl Phi//sub SQ2//d/spl Phi//sub SQ1/ in the range 30-70 and an overall flux-to-voltage transfer factor d/spl Phi//sub SQ2//d/spl Phi//sub SQ1/ as high as 3 mV//spl Phi//sub 0/ have been obtained. An effective input inductance L/sub IN/ equal to 1.8 /spl mu/H, a current sensitivity 1.33 /spl mu/A//spl Phi//sub 0/, and an effective coupling coefficient k/sup 2//sub IN/ close to 0.1 have been found in the accordance with the design.
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A description is given of the design, fabrication technology, and characteristics of a sensor for a scanning magnetic microscope using a thin-film dc SQUID with Nb/Al2O3/Nb shunted Josephson tunnel junctions. It is shown that at a sample... more
A description is given of the design, fabrication technology, and characteristics of a sensor for a scanning magnetic microscope using a thin-film dc SQUID with Nb/Al2O3/Nb shunted Josephson tunnel junctions. It is shown that at a sample temperature of 4.2 K the spatial resolution of this detector is 10 µm with a field resolution of 70 pT/Hz1/2.
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We have demonstrated a digital receiver performing direct digitization of radio-frequency signals over a wide frequency range from kilohertz to gigahertz. The complete system, consisting of a cryopackaged superconductor all-digital... more
We have demonstrated a digital receiver performing direct digitization of radio-frequency signals over a wide frequency range from kilohertz to gigahertz. The complete system, consisting of a cryopackaged superconductor all-digital receiver (ADR) chip followed by room-temperature interface electronics and a field programmable gate array (FPGA) based post-processing module, has been developed. The ADR chip comprises a low-pass analog-to-digital converter (ADC) delta modulator with phase modulation-demodulation architecture together with digital in-phase and quadrature mixer and a pair of digital decimation filters. The chip is fabricated using a 4.5 kA cm-2 process and is cryopackaged using a commercial-off-the-shelf cryocooler. Experimental results in HF, VHF, UHF and L bands and their analysis, proving consistent operation of the cryopackaged ADR chip up to 24.32 GHz clock frequency, are presented and discussed.
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Wireless applications would be less expensive, more flexible, and more robust if they had more digital and less analog circuitry. The problem is implementing digital signal processing at radio frequencies. Conventional data converters... more
Wireless applications would be less expensive, more flexible, and more robust if they had more digital and less analog circuitry. The problem is implementing digital signal processing at radio frequencies. Conventional data converters (ADCs and DACs) and digital circuits are simply not fast enough, especially at SATCOM frequencies. However, superconductors can provide ultra fast mixed signal and digital circuits with the linearity and dynamic range required for true direct, digital-RF processing. These superconducting circuits are digital ICs based on Josephson junctions and "rapid-single-flux-quantum" logic (RSFQ), where simple circuit switching speeds up to 750 GHz have been demonstrated. This permits direct conversion between analog RF and digital baseband signals, replacing frequency and protocol-specific analog hardware with flexible digital processors. HYPRES recently developed and delivered an X-band All Digital RF Receiver (XADR) prototype system for the US Army CERDEC and PM DCATS. The concept of this ADR is to replace the entire analog RF receive chain between the antenna and the baseband demodulator with a high performance digital RF equivalent. The first XADR prototype system has been successfully demonstrated at the Joint SATCOM engineering Center (JSEC). End to end link testing, over the satellite has been successfully completed using an existing AN/GSC-39 X-band earth terminal, an XTAR satellite, the X-band ADR and a SATCOM modem.
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We present a novel, resistor-free approach to dc biasing of RSFQ circuits, known as Energy-efficient RSFQ (ERSFQ). This biasing scheme does not dissipate energy in the static (non-active) mode, and dissipates orders of magnitude less... more
We present a novel, resistor-free approach to dc biasing of RSFQ circuits, known as Energy-efficient RSFQ (ERSFQ). This biasing scheme does not dissipate energy in the static (non-active) mode, and dissipates orders of magnitude less power than traditional RSFQ while operating. Using this approach, we have designed, fabricated and successfully tested at low and high speed a D flip-flop with complementary outputs and several static frequency dividers. We present the method, demonstrate experimental results, and discuss future implementations of ERSFQ.