In a power management integrated circuit (PMIC) documentation I came across a programmable dead-time parameter for a DC-DC converter.
What does dead-time of a DC-DC converter/regulator mean?
What role does it play a role in shaping the efficiency of the DC-DC converter?
The dead time is the period at which no part of a H-bridge driver is turned on.
It is used when you have two complementary PWM signals (one on when the other is off) so that neither the high nor the low side of the H-bridge can be conducting at once.
In this waveform it is the grey areas between one signal turning off and the other one turning on.
Since a MOSFET never instantly goes from ON to OFF, or OFF to ON, but instead has a gate charge and discharge time, if you don't include dead time in the waveforms it is possible for one MOSFET to turn on while the other is still in the process of turning off. This gives a low resistance path direct across the power supply, which is a very very Bad Idea™.
For a more realistic view, here's some timing diagrams. As you can see, in the first one, the PWML signal is starting to turn on whilst the PWMH signal is still in the process of turning off. The rise and fall times cause a crossover. In the second one the dead time ensures that PWMH has fully turned off before PWML starts to turn on.
Being able to configure that dead time is important. The more dead time you have the less efficient your converter will be, since during that period it's not actually doing anything at all. But, if the dead time is too short you suffer the shoot through problem and things get messy very rapidly. So tuning it to match the characteristics of the output stage (MOSFET or IGBT, for instance) means you can balance the efficiency to shoot through nicely.
Majenkos answer is absolutely correct in every situation except for the common boost, buck, and buck boost designs. Smaller single channel PWM circuits like these don't have an H bridge, and don't experience shoot through.
In these applications, the dead time input can be used as part of the feedback and control paths. For instance, on chips capable of a true 100% duty cycle, the dead time input can be set so that there must be a fixed period of time after each cycle before the next cycle starts, ensuring that the signal doesn't get stuck high in some conditions.
Another trick used with that dead time input is to hand control of it to a microcontroller. Normally, the duty cycle of the system is set by a closed loop feedback to a built in reference - by allowing an external source to control the maximum duty cycle generated, it can be used to zero out the duty cycle in certain conditions, for instance, during an overload. In most cases I've seen it can be digitally controlled directly using TTL voltages, so a logic low simply disables the duty cycle.
