V380SDC-75A0 datasheet - Specifications: Device Type: DRAM CONTROLLER ; Supply

Details, datasheet, quote on part number: V380SDC-75A0
PartV380SDC-75A0
CategoryCommunication and Interfaces => IC Interfaces => IC Interfaces
Title2G X 8, DRAM CONTROLLER, PQFP100
Description
CompanyQuickLogic Corp
DatasheetDownload V380SDC-75A0 Datasheet
Specifications 
Device TypeDRAM CONTROLLER
Supply Voltage3.3V
Operating Temperature-40 to 85 C (-40 to 185 F)
Package TypeQFP, EIAJ, PLASTIC, QFP-100
Pins100

 

Features, Applications

w Direct interface to these processors: AMD� AM29030/40TM IBM� PowerPC 401TM Gx IDT� 79RC32364TM Intel� i960� Cx/Hx/Jx/Rx/Vx Motorola� M68040TM and 68K/ColdFire� PowerPCTM to 75 MHz local bus clock w 8-bit bus watch timer to 2 Kbytes of continuous burst access for 64-bit processors and 1 Kbyte for 32-bit processors w Zero-wait-state bursting w Dynamic bus protocol switching w User-customized processor bus interface w Support for to 2 Gbytes of (Enhanced) SDRAM w Compatible with PC100, PC133 SDRAM w Supports a wide range of synchronous DRAMs, from 16 Mbit to 256 Mbit w System heartbeat and watchdog timers w Two 32-bit general purpose timers with pulsewidth modulation capability--useful for RTOS 16-bytes of general purpose registers w Designed to work with the EPC family of PCI bridges from V3 Semiconductor 3.3 V operation with 5 V tolerant inputs w Industrial temperature range +85�C) w Low-cost 100-pin PQFP package w Support for to 4 single-bank or 2 dual-bank industry standard 168-pin SDRAM DIMM(s) or 144-pin SO-DIMM(s) w I2C EEPROM interface for Serial Presence Detect (SPD) on DIMM w Optional EEPROM initialization

The V380SDC High Performance SDRAM Controller provides all aspects of SDRAM control for high performance embedded systems. The V380SDC enables system designers to replace many lower integration support components with a single, high-integration device. This saves design time, board space, and manufacturing cost. The V380SDC from V3 Semiconductor provides the necessary (Enhanced) SDRAM access protocol and bus timing resources to work with the latest (E)SDRAM devices. The processor interface on the V380SDC implements the bus protocol of many popular RISC CPUs (AM29030/40, PowerPC 401 Gx, IDT 79RC32364, i960 Cx/Hx/Jx/Rx/Vx, M68040, 68K/ColdFire, PowerPC 750/60x). The V380SDC is also fully compatible with the EPC family of PCI bridges available from V3 Semiconductor. The V380SDC supports a total SDRAM memory subsystem size to 2 Gbytes. Standard memory devices from 16 Mbit to 256 Mbit are supported; 16-, 32-bit and 64-bit accesses are allowed. Four single-bank or two dualbank industry standard 168-pin PC SDRAM DIMM(s) or 144-pin SO-DIMM(s) with Serial Presence Detect (SPD) are also supported. The V380SDC provides an 8-bit bus watch timer to detect and recover from accesses to unpopulated memory regions. Two on-chip, general purpose, 32-bit timers can be individually configured as a pulse width modulator or they may be used in other modes such as retriggerable or one-shot. The V380SDC is packaged in a low-cost 100-pin EIJA Plastic Quad Flat Pack (PQFP), and is available in 75 MHz speed grade. This document contains the product codes, pinout, package mechanical information, DC characteristics, and AC characteristics for the V380SDC. Detailed functional information is contained in the User's Manual. Figure 1: Example Application

V3 Semiconductor retains the rights to change the documentation, the specifications, or device functionality at any time without notice. Contact V3 and verify that you have the latest copy of all documents before finalizing a design.

Product Code V380SDC-75 REV A0 Package 100-pin EIAJ PQFP Frequency 75 MHz

Table 2 lists the pin types found on the V380SDC; Table 3 describes the function of each pin. Table 2: Pin Types

Pin Type I/O8 I/OD O8 O12 Description TTL I/O pin with 8 mA output drive. TTL input with open drain output. TTL input only pin. TTL open drain output. TTL output pin with 8 mA output drive. TTL output pin with 12 mA output drive.


 

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