Object Code Compatible with Earlier TS68000 Microprocessors Addressing Mode Extensions for Enhanced Support of High Level Languages New Bit Field Data Type Accelerates Bit-oriented Application, i.e. Video Graphics Fast on-chip Instruction Cache Speed Instructions and Improves Bus Bandwidth Co-processor Interface to Companion 32-bit Peripherals: TS68881 and TS68882 Floating Point Co-processors Pipelined Architecture with High Degree of Internal Parallelism Allowing Multiple Instructions to be Executed Concurrently High Performance Asynchronous Bus in Non-multiplexed and Full 32 Bits Dynamic Bus Sizing Efficiently Supports 16-, 32-bit Memories and Peripherals Full Support of Virtual Memory and Virtual Machine Sixteen 32-bit General-purpose Data and Address Registers Two 32-bit Supervisor Stack Pointers and 5 Special Purpose Control Registers 18 Addressing Modes and 7 Data Types 4-Gbyte Direct Addressing Range Processor Speed: 16.67 MHz - 20 MHz - 25 MHz Power Supply: 5.0 VDC � 10%

The TS68020 is the first full 32-bit implementation of the TS68000 family of microprocessors. Using HCMOS technology, the TS68020 is implemented with 32-bit registers and data paths, 32-bit addresses, a rich instruction set, and versatile addressing modes.

This product is manufactured in full compliance with either: MIL-STD-883 (class B) DESC 860320 or according to Atmel standards

The is a high-performance 32-bit microprocessor. It is the first microprocessor to have evolved from a 16-bit machine to a full 32-bit machine that provides 32-bit address and data buses as well as 32-bit internal structures. Many techniques were utilized to improve performance and at the same time maintain compatibility with other processors of the TS68000 Family. Among the improvements are new addressing modes which better support high-level language structures, an expanded instruction set which provides 32-bit operations for the limited cases not supported by the TS68000 and several new instructions which support new data types. For special-purpose applications when a general-purpose processor alone is not adequate, a co-processor interface is provided. The is a high-performance microprocessor implemented in HCMOS, low power, small geometry process. This process allows CMOS and HMOS (high density NMOS) gates to be combined on the same device. CMOS structures are used where speed and low power is required, and HMOS structures are used where minimum silicon area is desired. This technology enables the to be very fast while consuming less power (less than 1.5 watts) and still have a reasonably small die size. It utilizes about 190.000 transistors, 103.000 of which are actually implemented. The package is a pin-grid array (PGA) with 114 pins, arranged 13 pins on a side with a depopulated center and 132 pins ceramic quad flat pack. Figure is a block diagram of the TS68020. The processor can be divided into two main sections: the bus controller and the micromachine. This division reflects the autonomy with which the sections operate.

The bus controller consists of the address and data pads and multiplexers required to support dynamic bus sizing, a macro bus controller which schedules the bus cycles on the basis of priority with two state machines (one to control the bus cycles for operated accesses and the other to control the bus cycles for instruction accesses), and the instruction cache with its associated control.

The micromachine consists of an execution unit, nanorom and microrom storage, an instruction decoder, an instruction pipe, and associated control sections. The execution unit consists of an address section, an operand address section, and a data section. Microcode control is provided by a modified two-level store of microrom and nanorom. Programmed logical arrays (PLAs) are used to provide instruction decode and sequencing information. The instruction pipe and other individual control sections provide the secondary decode of instructions and generated the actual control signals that result in the decoding and interpretation of nanorom and micorom information. Figure 2. PGA Terminal Designation