TMS320C31, TMS320LC31 Datasheet by Texas Instruments
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*9 TEXAS
INSTRUMENTS
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B – MARCH 1996 – REVISED JANUARY 1999
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
High-Performance Floating-Point Digital
Signal Processor (DSP):
– TMS320C31-80 (5 V)
25-ns Instruction Cycle Time
440 MOPS, 80 MFLOPS, 40 MIPS
– TMS320C31-60 (5 V)
33-ns Instruction Cycle Time
330 MOPS, 60 MFLOPS, 30 MIPS
– TMS320C31-50 (5 V)
40-ns Instruction Cycle Time
275 MOPS, 50 MFLOPS, 25 MIPS
– TMS320C31-40 (5 V)
50-ns Instruction Cycle Time
220 MOPS, 40 MFLOPS, 20 MIPS
– TMS320LC31-40 (3.3 V)
50-ns Instruction Cycle Time
220 MOPS, 40 MFLOPS, 20 MIPS
– TMS320LC31-33 (3.3 V)
60-ns Instruction Cycle Time
183.7 MOPS, 33.3 MFLOPS, 16.7 MIPS
32-Bit High-Performance CPU
16-/32-Bit Integer and 32-/40-Bit
Floating-Point Operations
32-Bit Instruction Word, 24-Bit Addresses
Two 1K × 32-Bit Single-Cycle Dual-Access
On-Chip RAM Blocks
Boot-Program Loader
On-Chip Memory-Mapped Peripherals:
– One Serial Port
– Two 32-Bit Timers
– One-Channel Direct Memory Access
(DMA) Coprocessor for Concurrent I/O
and CPU Operation
Fabricated Using 0.6 µm Enhanced
Performance Implanted CMOS (EPIC)
Technology by Texas Instruments (TI)
132-Pin Plastic Quad Flat Package
(PQ Suffix)
Eight Extended-Precision Registers
Two Address Generators With Eight
Auxiliary Registers and Two Auxiliary
Register Arithmetic Units (ARAUs)
Two Low-Power Modes
Two- and Three-Operand Instructions
Parallel Arithmetic/Logic Unit (ALU) and
Multiplier Execution in a Single Cycle
Block-Repeat Capability
Zero-Overhead Loops With Single-Cycle
Branches
Conditional Calls and Returns
Interlocked Instructions for
Multiprocessing Support
Bus-Control Registers Configure
Strobe-Control Wait-State Generation
description
The TMS320C31 and TMS320LC31 DSPs are 32-bit, floating-point processors manufactured in 0.6 µm
triple-level-metal CMOS technology. The TMS320C31 and TMS320LC31 are part of the TMS320C3x
generation of DSPs from Texas Instruments.
The TMS320C3x’s internal busing and special digital-signal-processing instruction set have the speed and
flexibility to execute up to 80 million floating-point operations per second (MFLOPS). The TMS320C3x
optimizes speed by implementing functions in hardware that other processors implement through software or
microcode. This hardware-intensive approach provides performance previously unavailable on a single chip.
The TMS320C3x can perform parallel multiply and ALU operations on integer or floating-point data in a single
cycle. Each processor also possesses a general-purpose register file, a program cache, dedicated ARAUs,
internal dual-access memories, one DMA channel supporting concurrent I/O, and a short machine-cycle time.
High performance and ease of use are results of these features.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
EPIC and TI are trademarks of Texas Instruments Incorporated.
Copyright 1999, Texas Instruments Incorporated
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DIGITAL SIGNAL PROCESSORS
SPRS035B – MARCH 1996 – REVISED JANUARY 1999
2POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
description (continued)
General-purpose applications are greatly enhanced by the large address space, multiprocessor interface,
internally and externally generated wait states, one external interface port, two timers, one serial port, and
multiple-interrupt structure. The TMS320C3x supports a wide variety of system applications from host
processor to dedicated coprocessor.
High-level-language support is easily implemented through a register-based architecture, large address space,
powerful addressing modes, flexible instruction set, and well-supported floating-point arithmetic.
TMS320C31 and TMS320LC31 pinout (top view)
The TMS320C31 and TMS320LC31 devices are packaged in 132-pin plastic quad flatpacks (PQ Suffix).
D0
H1
A8
A7
A5
VDD
A4
A3
A2
A1
A0
VSS
D31
VDD
VDD
D30
VSS
VSS
D29
D28
VDD
D27
VSS
D26
D25
D24
D23
D22
D21 VSS
X2/CLKIN
HOLDA
HOLD
VDD
RDY
STRB
R/W
RESET
XF0
VDD
XF1
IACK
INT0
VSS
VSS
VDD
VDD
INT2
INT3
DR0
VSS
FSR0
CLKR0
CLKX0
VSS
FSX0
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
36
50
49
48
47
46
45
44
43
42
41
40
39
38
37
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
DD
V
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
SS
V
SS
V
51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 80 81 82 83
DD
V
DD
V
A22
A23
MCBL/MP
EMU2
EMU1
EMU0
EMU3
TCLK1
SHZ
DD
V
D18
D16
D15
D14
D13
D12
D11
D9
D10
D7
D6
D5
D4
D3
DD
V
DD
V
D8
SS
V
H3
79
A9
VSS
A6
VSS
VDD
D20
A10D19
D2
D1
VDD
DX0
INT1
X1
SS
V
A11
DD
V
SS
V
TCLK0
SS
V
SS
V
VSS
VSS
SS
V
D17
SS
V
DD
V
SS
V
SS
V
SS
V
DD
V
DD
V
PQ PACKAGE
(TOP VIEW)
VDD
Vss
VDD
Vss
VDD
Vss
Vss
VDD
Vss
*5 TEXAS
INSTRUMENTS
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B – MARCH 1996 – REVISED JANUARY 1999
3
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C31 and TMS320LC31 Terminal Assignments (Alphabetical)†
TERMINAL TERMINAL TERMINAL TERMINAL TERMINAL
NAME NO. NAME NO. NAME NO. NAME NO. NAME NO.
A0 29 D4 76 EMU0 124 VDD 40 VSS 84
A1 28 D5 75 EMU1 125 VDD 49 VSS 85
A2 27 D6 73 EMU2 126 VDD 59 VSS 86
A3 26 D7 72 EMU3 123 VDD 65 VSS 101
A4 25 D8 68 FSR0 110 VDD 66 VSS 102
A5 23 D9 67 FSX0 114 VDD 74 VSS 109
A6 22 D10 64 H1 81 VDD 83 VSS 113
A7 21 D11 63 H3 82 VDD 91 VSS 117
A8 20 D12 62 HOLD 90 VDD 97 VSS 119
A9 18 D13 60 HOLDA 89 VDD 104 VSS 128
A10 16 D14 58 IACK 99 VDD 105 X1 88
A11 14 D15 56 INT0 100 VDD 115 X2/CLKIN 87
A12 13 D16 55 INT1 103 VDD 121 XF0 96
A13 12 D17 54 INT2 106 VDD 131 XF1 98
A14 11 D18 53 INT3 107 VDD 132
A15 10 D19 52 MCBL/MP 127 VSS 3
A16 9 D20 50 RDY 92 VSS 4
A17 8 D21 48 RESET 95 VSS 17
A18 7 D22 47 R/W 94 VSS 19
A19 5 D23 46 SHZ 118 VSS 30
A20 2 D24 45 STRB 93 VSS 35
A21 1 D25 44 TCLK0 120 VSS 36
A22 130 D26 43 TCLK1 122 VSS 37
A23 129 D27 41 VSS 42
CLKR0 111 D28 39 VSS 51
CLKX0 112 D29 38 VDD 6 VSS 57
D0 80 D30 34 VDD 15 VSS 61
D1 79 D31 31 VDD 24 VSS 69
D2 78 DR0 108 VDD 32 VSS 70
D3 77 DX0 116 VDD 33 VSS 71
†VDD and VSS pins are on a common plane internal to the device.
V55 V00
VDD Vss
VDD VDD
Vss VDD
Vss
*9 TEXAS
INSTRUMENTS
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B – MARCH 1996 – REVISED JANUARY 1999
4POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C31 and TMS320LC31 Terminal Assignments (Numerical)†
TERMINAL TERMINAL TERMINAL TERMINAL TERMINAL
NO. NAME NO. NAME NO. NAME NO. NAME NO. NAME
1 A21 31 D31 61 VSS 91 VDD 121 VDD
2A20 32 VDD 62 D12 92 RDY 122 TCLK1
3 VSS 33 VDD 63 D11 93 STRB 123 EMU3
4 VSS 34 D30 64 D10 94 R/W 124 EMU0
5 A19 35 VSS 65 VDD 95 RESET 125 EMU1
6 VDD 36 VSS 66 VDD 96 XF0 126 EMU2
7 A18 37 VSS 67 D9 97 VDD 127 MCBL/MP
8 A17 38 D29 68 D8 98 XF1 128 VSS
9A16 39 D28 69 VSS 99 IACK 129 A23
10 A15 40 VDD 70 VSS 100 INT0 130 A22
11 A14 41 D27 71 VSS 101 VSS 131 VDD
12 A13 42 VSS 72 D7 102 VSS 132 VDD
13 A12 43 D26 73 D6 103 INT1
14 A11 44 D25 74 VDD 104 VDD
15 VDD 45 D24 75 D5 105 VDD
16 A10 46 D23 76 D4 106 INT2
17 VSS 47 D22 77 D3 107 INT3
18 A9 48 D21 78 D2 108 DR0
19 VSS 49 VDD 79 D1 109 VSS
20 A8 50 D20 80 D0 110 FSR0
21 A7 51 VSS 81 H1 111 CLKR0
22 A6 52 D19 82 H3 112 CLKX0
23 A5 53 D18 83 VDD 113 VSS
24 VDD 54 D17 84 VSS 114 FSX0
25 A4 55 D16 85 VSS 115 VDD
26 A3 56 D15 86 VSS 116 DX0
27 A2 57 VSS 87 X2/CLKIN 117 VSS
28 A1 58 D14 88 X1 118 SHZ
29 A0 59 VDD 89 HOLDA 119 VSS
30 VSS 60 D13 90 HOLD 120 TCLK0
†VDD and VSS pins are on a common plane internal to the device.
TVPE?
DESCRIPTION
WHEN
*5 TEXAS
INSTRUMENTS
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B – MARCH 1996 – REVISED JANUARY 1999
5
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C31 and TMS320LC31 Terminal Functions
TERMINAL
TYPE†
DESCRIPTION
CONDITIONS
WHEN
NAME QTY
TYPE†
DESCRIPTION
WHEN
SIGNAL IS Z TYPE‡
PRIMARY-BUS INTERFACE
D31–D0 32 I/O/Z 32-bit data port S H R
A23–A0 24 O/Z 24-bit address port S H R
R/W 1 O/Z Read/write. R/ W is high when a read is performed and low when a write is performed
over the parallel interface. S H R
STRB 1 O/Z External-access strobe S H
RDY 1 I Ready. RDY indicates that the external device is prepared for a transaction
completion.
HOLD 1 I
Hold. When HOLD is a logic low, any ongoing transaction is completed. A23–A0,
D31–D0, STRB, and R/W are placed in the high-impedance state and all
transactions over the primary-bus interface are held until HOLD becomes a logic high
or until the NOHOLD bit of the primary-bus-control register is set.
HOLDA 1 O/Z
Hold acknowledge. HOLDA is generated in response to a logic low on HOLD. HOLDA
indicates that A23–A0, D31–D0, STRB, and R/W are in the high-impedance state
and that all transactions over the bus are held. HOLDA is high in response to a logic
high of HOLD or the NOHOLD bit of the primary-bus-control register is set.
S
CONTROL SIGNALS
RESET 1 I Reset. When RESET is a logic low, the device is in the reset condition. When RESET
becomes a logic high, execution begins from the location specified by the reset vector.
INT3–INT0 4 I External interrupts
IACK 1 O/Z Interrupt acknowledge. IACK is generated by the IACK instruction. IACK can be used
to indicate the beginning or the end of an interrupt-service routine. S
MCBL/MP 1 I Microcomputer boot-loader/microprocessor mode-select
SHZ 1 I
Shutdown high impedance. When active, SHZ shuts down the device and places all
pins in the high-impedance state. SHZ is used for board-level testing to ensure that
no dual-drive conditions occur. CAUTION: A low on SHZ corrupts the device memory
and register contents. Reset the device with SHZ high to restore it to a known
operating condition.
XF1, XF0 2 I/O/Z External flags. XF1 and XF0 are used as general-purpose I/Os or to support
interlocked processor instruction. S R
SERIAL PORT 0 SIGNALS
CLKR0 1 I/O/Z Serial port 0 receive clock. CLKR0 is the serial shift clock for the serial port 0 receiver. S R
CLKX0 1 I/O/Z Serial port 0 transmit clock. CLKX0 is the serial shift clock for the serial port 0
transmitter. S R
DR0 1 I/O/Z Data-receive. Serial port 0 receives serial data on DR0. S R
DX0 1 I/O/Z Data-transmit output. Serial port 0 transmits serial data on DX0. S R
FSR0 1 I/O/Z Frame-synchronization pulse for receive. The FSR0 pulse initiates the data-receive
process using DR0. S R
FSX0 1 I/O/Z Frame-synchronization pulse for transmit. The FSX0 pulse initiates the data-transmit
process using DX0. S R
TIMER SIGNALS
TCLK0 1 I/O/Z Timer clock 0. As an input, TCLK0 is used by timer 0 to count external pulses. As an
output, TCLK0 outputs pulses generated by timer 0. S R
TCLK1 1 I/O/Z Timer clock 1. As an input, TCLK0 is used by timer 1 to count external pulses. As an
output, TCLK1 outputs pulses generated by timer 1. S R
†I = input, O = output, Z = high-impedance state
‡S = SHZ active, H = HOLD active, R = RESET active
DESCRIPTION
*9 TEXAS
INSTRUMENTS
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B – MARCH 1996 – REVISED JANUARY 1999
6POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C31 and TMS320LC31 Terminal Functions (Continued)
TERMINAL
TYPE†
DESCRIPTION
CONDITIONS
WHEN
NAME QTY
TYPE†
DESCRIPTION
WHEN
SIGNAL IS Z TYPE‡
SUPPLY AND OSCILLATOR SIGNALS
H1 1 O/Z External H1 clock. H1 has a period equal to twice CLKIN. S
H3 1 O/Z External H3 clock. H3 has a period equal to twice CLKIN. S
VDD 20 I 5-V supply for ’C31 devices and 3.3-V supply for ’LC31 devices. All must be
connected to a common supply plane.§
VSS 25 I Ground. All grounds must be connected to a common ground plane.
X1 1 O Output from the internal-crystal oscillator. If a crystal is not used, X1 should be left
unconnected.
X2/CLKIN 1 I Internal-oscillator input from a crystal or a clock
RESERVED¶
EMU2–EMU0 3 I Reserved for emulation. Use pullup resistors to VDD
EMU3 1 O/Z Reserved for emulation S
†I = input, O = output, Z = high-impedance state
‡S = SHZ active, H = HOLD active, R = RESET active
§Recommended decoupling capacitor value is 0.1 µF.
¶Follow the connections specified for the reserved pins. Use 18-kΩ–22-kΩ pullup resistors for best results. All VDD supply pins must be connected
to a common supply plane, and all ground pins must be connected to a common ground plane.
NOTES: 1. A test mode for measuring leakage currents in the TMS320C31 is implemented. This test mode powers down the clock oscillator
circuit resulting in currents below 10 µA. The test mode is entered by asserting SHZ low, which tri–states all output pins and then
holds both H1 and H3 at logic high. The test mode is not intended for application use because it does not preserve the processor
state.
2. Since SHZ is a synchronized input and the clock is disabled, exiting the test mode occurs only when at least one of the H1/H3 pins
is pulled low. Reset cannot be used to wake up in test mode since the SHZ pin is sampled and the clocks are not running.
3. On power up, the processor can be in an indeterminate state. If the state is SHZ mode and H1 and H3 are both held logic high by
pull–ups, then shutdown will occur. Normally, if H1 and H3 do not have pull–ups, the rise time lag due to capacitive loading on a
tri–state pin is enough to ensure a clean start. However, a slowly rising supply and board leakages to VCC may be enough to cause
a bad start. Therefore, a pulldown resistor on either H1 or H3 is recommended for proper wakeup.
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*9 TEXAS
INSTRUMENTS
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B – MARCH 1996 – REVISED JANUARY 1999
7
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
functional block diagram
24
Boot
Loader
Cache
(64 × 32)
RAM
Block 0
(1K × 32)
RAM
Block 1
(1K × 32)
RDY
HOLD
HOLDA
STRB
R/W
D31– D0
A23 – A0
RESET
IR
PC CPU1
REG1
REG2
MUX
40
32
32
32
32
32
32
32
24
24
24
24
BK
ARAU0 ARAU1
DISP0, IR0, IR1
Extended-
Precision
Registers
(R7–R0)
Auxiliary
Registers
(AR0 – AR7)
Other
Registers
(12)
40
40
40
40
Multiplier
32-Bit
Barrel
Shifter
ALU
DMA Controller
Global-Control
Register
Source-Address
Register
Destination-
Address
Register
Serial Port 0
Serial-Port-Control
Register
Receive/Transmit
(R / X) Timer Register
Data-Transmit
Register
Data-Receive
Register
FSX0
DX0
CLKX0
FSR0
DR0
CLKR0
Timer 0
Global-Control
Register
Timer-Period
Register
Timer-Counter
Register
TCLK0
Timer 1
Global-Control
Register
Timer-Period
Register
Timer-Counter
Register
TCLK1
Port Control
STRB-Control
Register
Transfer-
Counter
Register
PDATA Bus
PADDR Bus
DDATA Bus
DADDR1 Bus
DADDR2 Bus
DMADATA Bus
DMAADDR Bus
24
40
32 32 24 24 32
INT(3 – 0)
IACK
MCBL / MP
XF(1,0)
VDD(19 – 0)
VSS(24 – 0)
X1
X2 / CLKIN
H1
H3
EMU(3 – 0)
32 24 24 24 2432 32 32
CPU2
32 32 40 40
MUX
Controller
Peripheral Data Bus
Peripheral Address Bus
CPU1
REG1
REG2
MUX
anau
Exle
Exle
*9 TEXAS
INSTRUMENTS
Emma
Exle
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B – MARCH 1996 – REVISED JANUARY 1999
8POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
memory map
Peripheral Bus
Memory-Mapped Registers
(6K Words Internal)
Reset, Interrupt, Trap Vector, and
Reserved Locations (64)
(External STRB Active)
0h
03Fh
040h
External
STRB Active
(8M Words – 64 Words)
7FFFFFh
Reserved
(32K Words)
800000h
807FFFh
808000h
8097FFh
RAM Block 0
(1K Words Internal)
809800h
809BFFh
809C00h
809FFFh
80A000h External
STRB Active
(8M Words – 40K Words)
FFFFFFh
0h
FFFh
1000h
7FFFFFh
Reserved
(32K Words)
800000h
807FFFh
Peripheral Bus
Memory-Mapped Registers
(6K Words Internal)
808000h
8097FFh
RAM Block 0
(1K Words Internal)
809800h
809BFFh
809C00h
809FFFh
80A000h External
STRB Active
(8M Words –
40K Words)
FFFFFFh
Boot 1
Boot 2
400000h
RAM Block 1
(1K Words – 63 Words Internal)
809FC0h
809FC1h User-Program Interrupt
and Trap Branches
(63 Words Internal)
Boot 3
FFF000h
External
STRB
Active
(8M Words –
4K Words)
Reserved for Boot-Loader
Operations
(a) Microprocessor Mode (b) Microcomputer/Boot-Loader Mode
RAM Block 1
(1K Words Internal)
Figure 1. TMS320C31 Memory Maps
*5 TEXAS
INSTRUMENTS
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B – MARCH 1996 – REVISED JANUARY 1999
9
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
memory map (continued)
Reset
00h INT0
809FC1h
INT1
01h INT1
809FC2h
INT2
02h INT2
809FC3h
INT3
03h INT3
809FC4h
XINT0
04h
XINT0
809FC5h
RINT0
06h RINT0
809FC6h
Reserved
07h Reserved
809FC7h
809FC8h
08h
TINT0
09h TINT0809FC9h
TINT1
0Ah TINT1
809FCAh
DINT
0Bh DINT
809FCBh
Reserved
0Ch Reserved
809FDFh
1Fh 809FCCh
TRAP 020h TRAP 0
809FE0h
TRAP 273Bh TRAP 27809FFBh
Reserved
3Ch Reserved
809FFFh
3Fh
809FFCh
(a) Microprocessor Mode (b) Microcomputer/Boot-Loader Mode
INT0
05h
Figure 2. Reset, Interrupt, and Trap Vector/Branches Memory-Map Locations
*9 TEXAS
INSTRUMENTS
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B – MARCH 1996 – REVISED JANUARY 1999
10 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
memory map (continued)
FSX/DX/CLKX Serial Port Control
FSR/DR/CLKR Serial Port Control
Serial R/X Timer Control
Serial R/X Timer Counter
Serial R/X Timer Period Register
Data-Transmit
Data-Receive
Primary-Bus Control
DMA Global Control
DMA Source Address
DMA Destination Address
DMA Transfer Counter
Timer 0 Global Control
Timer 0 Counter
Timer 0 Period Register
Timer 1 Global Control
Timer 1 Counter
Timer 1 Period Register
Serial Global Control
808000h
808004h
808006h
808008h
808020h
808024h
808028h
808030h
808034h
808038h
808040h
808042h
808043h
808044h
808045h
808046h
808048h
80804Ch
808064h
†Shading denotes reserved address locations
Figure 3. Peripheral Bus Memory-Mapped Registers†
*5 TEXAS
INSTRUMENTS
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B – MARCH 1996 – REVISED JANUARY 1999
11
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
absolute maximum ratings over specified temperature range (unless otherwise noted)†
’C31 ’LC31
Supply voltage range, VDD (see Note 1) –0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 5 V. . . . . . . . . .
Input voltage range, VI –0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 5 V. . . . . . . . . .
Output voltage range, VO –0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 5 V. . . . . . . . . .
Continuous power dissipation (worst case) (see Note 5) 2.6 W. . . . . . . . . . . . . . . . . .
(for TMS320C31-80) 850 mW. . . . . . . . . . . . . .
(for TMS320LC31-33)
Operating case temperature range, TCPQL (commercial) 0°C to 85°C. . . . . . . . 0°C to 85°C. . . . . . . . . . .
PQA (industrial) – 40°C to 125°C. . . . . . .
Storage temperature range, Tstg – 55°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 150°C. . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 4. All voltage values are with respect to VSS.
5. Actual operating power is less. This value was obtained under specially produced worst-case test conditions for the TMS320C31,
which are not sustained during normal device operation. These conditions consist of continuous parallel writes of a checkerboard
pattern to both primary and extension buses at the maximum rate possible. See normal (ICC) current specification in the electrical
characteristics table and also read
Calculation of TMS320C30 Power Dissipation Application Report
(literature number SPRA020)
.
recommended operating conditions (see Note 6)
’C31 ’LC31
UNIT
MIN NOM MAX MIN NOM MAX
UNIT
VDD Supply voltage (DVDD, etc.) 4.75 5 5.25 3.13 3.3 3.47 V
VSS Supply voltage (CVSS, etc.) 0 0 V
VIH High-level input voltage 2 VDD + 0.3‡1.8 VDD + 0.3‡V
VIL Low-level input voltage – 0.3‡0.8 – 0.3‡0.6 V
IOH High-level output current – 300 – 300 µA
IOL Low-level output current 2 2 mA
TCOperating case temperature (commercial) 0 85 0 85 °C
Operating case temperature (industrial) – 40 125 °C
VTH High-level input voltage for CLKIN 2.6 VDD + 0.3‡2.5 VDD + 0.3‡V
‡These values are derived from characterization and not tested.
NOTE 6: All voltage values are with respect to VSS. All input and output voltage levels are TTL-compatible. CLKIN can be driven by a CMOS
clock.
PARAMETER
TEST CONDITIONS
VDD ‘OH
VDD ‘OH
VDD
V\ $3 to VDD
v :33 MH~ 1031 33
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B – MARCH 1996 – REVISED JANUARY 1999
12 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
electrical characteristics over recommended ranges of supply voltage (unless otherwise noted)
(see Note 3)†
PARAMETER
TEST CONDITIONS
’C31 ’LC31
UNIT
PARAMETER
TEST
CONDITIONS
MIN TYP‡MAX MIN TYP‡MAX
UNIT
VOH High-level output voltage VDD = MIN, IOH = MAX 2.4 3 2 V
VOL Low-level output voltage VDD = MIN, IOH = MAX 0.3 0.6 0.4 V
IZHigh-impedance current VDD = MAX – 20 + 20 – 20 + 20 µA
IIInput current VI = VSS to VDD – 10 + 10 – 10 + 10 µA
IIP Input current (with internal
pullup) Inputs with internal pullups§– 600 20 – 600 10 µA
¶#
f = 33 MHz
’
LC31 33
150
325
120
250
¶#
f
x =
33
MH
z
’LC31
-
33
150
325
120
250
¶#
T25°C
fx = 33 MHz ’C31-33
(ext. temp) 150 325
ICC Supply current
¶#
TA = 25°C,
VDD = MAX
fx = 40 MHz ’C31-40 160 390 150 300 mA
CC
y
VDD
=
MAX
fx = 50 MHz ’C31-50 200 425
fx = 60 MHz ’C31-60 225 475
fx = 80 MHz ’C31-80 275 550
IDD Supply current Standby, IDLE2 Clocks shut off 50 20 µA
Ci
Input All inputs except CLKIN 15|| 15|| p
F
C
icapacitance CLKIN 25 25
pF
CoOutput capacitance 20|| 20|| pF
†All input and output voltage levels are TTL compatible.
‡For ’C31, all typical values are at VDD = 5 V, TA (air temperature) = 25°C. For ’LC31, all typical values are at VDD = 3.3 V,
TA (air temperature) = 25°C.
§Pins with internal pullup devices: INT3–INT0, MCBL/MP.
¶Actual operating current is less than this maximum value. This value was obtained under specially produced worst-case test conditions, which
are not sustained during normal device operation. These conditions consist of continuous parallel writes of a checkerboard pattern at the
maximum rate possible. See
Calculation of TMS320C30 Power Dissipation Application Report
(literature number SPRA020).
#fx is the input clock frequency.
|| Specified by design but not tested
NOTE 6: All voltage values are with respect to VSS. All input and output voltage levels are TTL-compatible. CLKIN can be driven by a CMOS
clock.
Test
*9 TEXAS
INSTRUMENTS
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TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
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13
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
PARAMETER MEASUREMENT INFORMATION
Tester Pin
Electronics VLoad
IOL
CT
IOH
Output
Under
Test
Where: IOL = 2 mA (all outputs)
IOH = 300 µA (all outputs)
VLOAD = 2.15 V
CT= 80-pF typical load-circuit capacitance
Figure 4. TMS320C31 Test Load Circuit
signal transition levels for ’C31 (see Figure 5 and Figure 6)
TTL-level outputs are driven to a minimum logic-high level of 2.4 V and to a maximum logic-low level of 0.6 V.
Output transition times are specified as follows:
For a high-to-low transition on a TTL-compatible output signal, the level at which the output is said to be
no longer high is 2 V and the level at which the output is said to be low is 1 V.
For a low-to-high transition, the level at which the output is said to be no longer low is 1 V and the level at
which the output is said to be high is 2 V.
0.6 V
1 V
2 V
2.4 V
Figure 5. TTL-Level Outputs
Transition times for TTL-compatible inputs are specified as follows:
For a high-to-low transition on an input signal, the level at which the input is said to be no longer high is
2 V and the level at which the input is said to be low is 0.8 V.
For a low-to-high transition on an input signal, the level at which the input is said to be no longer low is
0.8 V and the level at which the input is said to be high is 2 V.
2 V
0.8 V
Figure 6. TTL-Level Inputs
Tesl
*9 TEXAS
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TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B – MARCH 1996 – REVISED JANUARY 1999
14 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
PARAMETER MEASUREMENT INFORMATION
Tester Pin
Electronics VLoad
IOL
CT
IOH
Output
Under
Test
Where: IOL = 2 mA (all outputs)
IOH = 300 µA (all outputs)
VLOAD = 2.15 V
CT= 80-pF typical load-circuit capacitance
Figure 7. TMS320LC31 Test Load Circuit
signal transition levels for ’LC31 (see Figure 8 and Figure 9)
Outputs are driven to a minimum logic-high level of 2 V and to a maximum logic-low level of 0.4 V. Output
transition times are specified as follows:
For a high-to-low transition on an output signal, the level at which the output is said to be no longer high
is 2 V and the level at which the output is said to be low is 1 V.
For a low-to-high transition, the level at which the output is said to be no longer low is 1 V and the level at
which the output is said to be high is 2 V.
0.4 V
0.6 V
2 V
1.8 V
Figure 8. ’LC31 Output Levels
Transition times for inputs are specified as follows:
For a high-to-low transition on an input signal, the level at which the input is said to be no longer high is
1.8 V and the level at which the input is said to be low is 0.6 V.
For a low-to-high transition on an input signal, the level at which the input is said to be no longer low is
0.6 V and the level at which the input is said to be high is 1.8 V.
1.8 V
0.6 V
Figure 9. ’LC31 Input Levels
*9 TEXAS
INSTRUMENTS
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
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15
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
PARAMETER MEASUREMENT INFORMATION
timing parameter symbology
Timing parameter symbols used herein were created in accordance with JEDEC Standard 100-A. In order to
shorten the symbols, some of the pin names and other related terminology have been abbreviated as follows,
unless otherwise noted:
A A23–A0 H H1 and H3
ASYNCH Asynchronous reset signals HOLD HOLD
C CLKX0 HOLDA HOLDA
CI CLKIN IACK IACK
CLKR CLKR0 INT INT3–INT0
CONTROL Control signals RDY RDY
D D31–D0 RW R/ W
DR DR RESET RESET
DX DX S STRB
FS FSX/R SCK CLKX/R
FSX FSX0 SHZ SHZ
FSR FSR0 TCLK TCLK0, TCLK1, or TCLKx
GPI General-purpose input XF XF0, XF1, or XFx
GPIO General-purpose input/output; peripheral pin XFIO XFx switching from input to output
GPO General-purpose output
Won
New
won
WH)
NH)
*9 TEXAS
INSTRUMENTS
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
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timing
Timing specifications apply to the TMS320C31 and TMS320LC31.
X2/CLKIN, H1, and H3 timing
The following table defines the timing parameters for the X2/CLKIN, H1, and H3 interface signals. The numbers
shown in Figure 10 and Figure 11 correspond with those in the NO. column of the table below.
timing parameters for X2/CLKIN, H1, H3 (see Figure 10 and Figure 11)
NO. ’LC31 ’C31-40
’LC31-40 ’C31-50 ’C31-60 ’C31-80 UNIT
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
1 tf(CI) Fall time, CLKIN 5†5†5†4†4†ns
2 tw(CIL) Pulse duration, CLKIN
low tc(CI) = min 10 9 7 6 5 ns
3 tw(CIH) Pulse duration, CLKIN
high tc(CI) = min 10 9 7 6 5 ns
4 tr(CI) Rise time, CLKIN 5†5†5†4†4†ns
5 tc(CI) Cycle time, CLKIN 30 303 25 303 20 303 16.67 303 12.5 303 ns
6 tf(H) Fall time, H1 and H3 3 3 3 3 3 ns
7 tw(HL) Pulse duration, H1
and H3 low P–6‡P–5‡P–5‡P–4‡P–3‡ns
8 tw(HH) Pulse duration, H1
and H3 high P–7‡P–6‡P–6‡P–5‡P–4‡ns
9 tr(H) Rise time, H1 and H3 4 3 3 3 3 ns
10 td(HL-HH)
Delay time. from H1
low to H3 high or from
H3 low to H1 high 0 5 0 4 0 4 0 4 0 3 ns
11 tc(H) Cycle time, H1 and H3 60 606 50 606 40 606 33.3 606 25 606 ns
†Specified by design but not tested
‡P = tc(CI)
1
4
X2/CLKIN
3
5
2
Figure 10. Timing for X2/CLKIN
H3
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INSTRUMENTS
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
X2/CLKIN, H1, and H3 timing (continued)
H3
H1
6
9
10
10
6
9
11
78
7
8
11
Figure 11. Timing for H1 and H3
svxal Q‘
SLNHWHHLSNI
td H1 LVSL
td H1 LVSH
14:! H1 HVRWL R
td H1 LVA
tsu DrH1 L R
th H1 LVD R
tsu RDYVH1H
th H1 HVRDY
td H1 HVRWH W
tv H|LVD W
th H1 HVD W
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B – MARCH 1996 – REVISED JANUARY 1999
18 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
•
memory read/write timing
The following table defines memory read/write timing parameters for STRB. The numbers shown in Figure 12 and Figure 13 correspond with
those in the NO. column of the table below.
timing parameters for memory (STRB = 0) read/write (see Figure 12 and Figure 13)†
NO. ’LC31-33 ’C31-40
’LC31-40 ’C31-50 ’C31-60 ’C31-80 UNIT
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
12 td(H1L-SL) Delay time, H1 low to STRB low 0‡10 0‡6 0‡5 0‡5 0‡5 ns
13 td(H1L-SH) Delay time, H1 low to STRB high 0‡10 0‡6 0‡5 0‡5 0‡5 ns
14 td(H1H-RWL)R Delay time, H1 high to R/W low (read) 0‡10 0‡9 0‡7 0‡6 0‡4 ns
15 td(H1L-A) Delay time, H1 low to A valid 0‡14 0‡11 0‡9 0‡8 0‡7ns
16 tsu(D-H1L)R Setup time, D before H1 low (read) 16 14 10 9 8 ns
17 th(H1L-D)R Hold time, D after H1 low (read) 0 0 0 0 0 ns
18 tsu(RDY-H1H) Setup time, RDY before H1 high 8 8 6 5 4 ns
19 th(H1H-RDY) Hold time, RDY after H1 high 0 0 0 0 0 ns
20 td(H1H-RWH)W Delay time, H1 high to R/W high (write) 10 9 7 6 4 ns
21 tv(H1L-D)W Valid time, D after H1 low (write) 20 17 14 12 8 ns
22 th(H1H-D)W Hold time, D after H1 high (write) 0 0 0 0 0 ns
23 td(H1H-A)W Delay time, H1 high to A valid on back-to-back write
cycles (write) 18 15 12 10 8 ns
24 td(A-RDY) Delay time, RDY from A valid 8‡7‡6‡6‡P - 8§ns
24A Taa Address valid to data valid (read) 30 25 21 16 10 ns
†See Figure 14 for address bus timing variation with load capacitance greater than typical load-circuit capacitance (CT = 80 pF).
‡This value is characterized but not tested
§In earlier data sheets, this parameter was shown as an “at speed” value. It is in fact a synchronized signal and therefore relative to Tc(H) where P = tc(C1) = tc(H)/2.
/_
\/\ \/\ \
_/_\
\/
INSTRUMENTS
*4" TEXAS
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
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19
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
memory read/write timing (continued)
12
14
15
13
16 17
19
18
H3
H1
R/W
A
D
RDY
STRB
24
NOTE A: STRB remains low during back-to-back read operations.
Figure 12. Timing for Memory (STRB = 0) Read
14
12
RDY
D
A
R/W
STRB
H1
H3
20
22
23
18 19
21
15
13
Figure 13. Timing for Memory (STRB = 0) Write
*9 TEXAS
INSTRUMENTS
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
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20 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
memory read/write timing (continued)
4.00
3.50
3.00
2.50
2.00
1.50
1.00
0.50
10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100
Change in Load Capacitance, pF
Change in Address-Bus Timing, ns
Address-Bus Timing Variation Load Capacitance
NOTE A: 30 pF/ns slope
Figure 14. Address-Bus Timing Variation With Load Capacitance (see Note A)
td HaerFnL
tsu xFH-H L
XFO Pin 26 4
XF1 Pin : ‘ :
*9 TEXAS
INSTRUMENTS
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TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
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21
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
XF0 and XF1 timing when executing LDFI or LDII
The following tables define the timing parameters for XF0 and XF1 during execution of LDFI or LDII. The
numbers shown in Figure 15 correspond with those in the NO. column of the tables below.
timing parameters for XF0 and XF1 when executing LDFI or LDII for TMS320C31 (see Figure 15)
NO. ’LC31-33 ’C31-40
’LC31-40 ’C31-50 ’C31-60 ’C31-80 UNIT
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
25 td(H3H-XF0L) Delay time, H3 high to XF0 low 15 13 12 11 8 ns
26 tsu(XF1-H1L) Setup time, XF1 before H1 low 10 9 9 8 6 ns
27 th(H1L-XF1) Hold time, XF1 after H1 low 0 0 0 0 0 ns
H3
H1
STRB
R/W
A
D
RDY
XF0 Pin
XF1 Pin
Fetch
LDFI or LDII Decode Read Execute
25
26
27
Figure 15. Timing for XF0 and XF1 When Executing LDFI or LDII
\/
um
um
Mm
um
um
/\
R/W
D
V
R
INSTRUMENTS
{5" TEXAS
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B – MARCH 1996 – REVISED JANUARY 1999
22 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
XF0 timing when executing STFI and STII†
The following table defines the timing parameters for the XF0 pin during execution of STFI or STII. The number
shown in Figure 16 corresponds with the number in the NO. column of the table below.
timing parameters for XF0 when executing STFI or STII (see Figure 16)
NO. ’LC31-33 ’C31-40
’LC31-40 ’C31-50 ’C31-60 ’C31-80 UNIT
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
28 td(H3H-XF0H) Delay time, H3 high to XF0
high 15 13 12 11 8 ns
†XF0 is always set high at the beginning of the execute phase of the interlock-store instruction. When no pipeline conflicts occur, the address of
the store is also driven at the beginning of the execute phase of the interlock-store instruction. However, if a pipeline conflict prevents the store
from executing, the address of the store will not be driven until the store can execute.
H3
H1
STRB
R/W
A
D
RDY
XF0 Pin
Fetch
STFI or STII Read Execute
28
Decode
Figure 16. Timing for XF0 When Executing an STFI or STII
4*\/
\1/\
/\/{\
1 ‘
\ \
fr:
*9 TEXAS
INSTRUMENTS
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B – MARCH 1996 – REVISED JANUARY 1999
23
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
XF0 and XF1 timing when executing SIGI
The following tables define the timing parameters for the XF0 and XF1 pins during execution of SIGI. The
numbers shown in Figure 17 correspond with those in the NO. column of the tables below.
timing parameters for XF0 and XF1 when executing SIGI for TMS320C31 (see Figure 17)
NO. ’LC31-33 ’C31-40
’LC31-40 ’C31-50 ’C31-60 ’C31-80 UNIT
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
29 td(H3H-XF0L) Delay time, H3 high to XF0
low 15 13 12 11 8 ns
30 td(H3H-XF0H) Delay time, H3 high to XF0
high 15 13 12 11 8 ns
31 tsu(XF1-H1L) Setup time, XF1 before H1
low 10 9 9 8 6 ns
32 th(H1L-XF1) Hold time, XF1 after H1 low 0 0 0 0 0 ns
H3
H1
Fetch
SIGI Decode Read Execute
XF0
XF1
31
32
29 30
Figure 17. Timing for XF0 and XF1 When Executing SIGI
24
XFX Pin
*9 TEXAS
INSTRUMENTS
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TMS320C31, TMS320LC31
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loading when XF is configured as an output
The following table defines the timing parameter for loading the XF register when the XFx pin is configured as
an output. The number shown in Figure 18 corresponds with the number in the NO. column of the table below.
timing parameters for loading the XF register when configured as an output pin (see Figure 18)
NO. ’LC31-33 ’C31-40
’LC31-40 ’C31-50 ’C31-60 ’C31-80 UNIT
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
33 tv(H3H-XF) Valid time, H3 high to XFx 15 13 12 11 8 ns
Fetch Load Decode Read Execute
H3
H1
OUTXFx Bit
(see Note A)
XFx Pin
1 or 0
33
Instruction
NOTE A: OUTXFx represents either bit 2 or 6 of the IOF register.
Figure 18. Timing for Loading XF Register When Configured as an Output Pin
/\L/\;/\
fi\fi\4\fl\/
/\
\
\1 /
\
\
\1
\
\
\/
Output
XFX
INXFx an
(see Note A)
*4" TEXAS
INSTRUMENTS
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
changing XFx from an output to an input
The following table defines the timing parameters for changing the XFx pin from an output pin to an input pin.
The numbers shown in Figure 19 correspond with those in the NO. column of the table below.
timing parameters of XFx changing from output to input mode for TMS320C31 (see Figure 19)
NO. ’LC31-33 ’C31-40
’LC31-40 ’C31-50 ’C31-60 ’C31-80 UNIT
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
34 th(H3H-XF) Hold time, XFx after
H3 high 15†13†12†11†9†ns
35 tsu(XF-H1L) Setup time, XFx
before H1 low 10 9 9 8 6 ns
36 th(H1L-XF) Hold time, XFx after
H1 low 00000ns
†This value is characterized but not tested.
Execute
Load of IOF
Buffers Go
From Output
to Output
Synchronizer
Delay Value on Pin
Seen in IOF
H3
H1
XFx Pin
INXFx Bit
(see Note A)
I/OxFx Bit
(see Note A)
34
35
36
Data
Sampled Data
Seen
Output
NOTE A: I/OxFx represents either bit 1 or bit 5 of the IOF register, and INXFx represents either bit 3 or bit 7 of the IOF register.
Figure 19. Timing for Change of XFx From Output to Input Mode
*9 TEXAS
INSTRUMENTS
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TMS320C31, TMS320LC31
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changing XFx from an input to an output
The following table defines the timing parameter for changing the XFx pin from an input pin to an output pin.
The number shown in Figure 20 corresponds with the number in the NO. column of the table below.
timing parameters of XFx changing from input to output mode (see Figure 20)
NO. ’LC31-33 ’C31-40
’LC31-40 ’C31-50 ’C31-60 ’C31-80 UNIT
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
37 td(H3H-XFIO) Delay time, H3 high to XFx
switching from input to output 20 17 17 16 9 ns
Execution of
Load of IOF
37
H3
H1
I/OxFx
Bit
(see Note A)
XFx Pin
NOTE A: I/OxFx represents either bit 1 or bit 5 of the IOF register.
Figure 20. Timing for Change of XFx From Input to Output Mode
reset timing
RESET is an asynchronous input that can be asserted at any time during a clock cycle. If the specified timings
are met, the exact sequence shown in Figure 21 occurs; otherwise, an additional delay of one clock cycle is
possible.
The asynchronous reset signals include XF0/1, CLKX0, DX0, FSX0, CLKR0, DR0, FSR0, and TCLK0/1.
The following table defines the timing parameters for the RESET signal. The numbers shown in Figure 21
correspond with those in the NO. column of the following table.
Resetting the device initializes the bus control register to seven software wait states and therefore results in slow
external accesses until these registers are initialized.
HOLD is an asynchronous input and can be asserted during reset.
1mm HVRWH)
44% dmx>m
EmiEZmzam
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B – MARCH 1996 - REVISED JANUARY 1999
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
•27
timing parameters for RESET for the TMS320C31 and TMS320LC31 (see Figure 21)
NO. ’LC31-33 ’C31-40
’LC31-40 ’LC31-40 ’C31-50 ’C31-60 ’C31-80 UNIT
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
38 tsu(RESET-CIL) Setup time, RESET before
CLKIN low 10 P†‡ 10 P†‡ 10 P†‡ 10 P†‡ 7 P†‡ 4 P†‡ ns
39 td(CLKINH-H1H) Delay time, CLKIN high to H1
high§2 12 2 12¶2 14 2 10 2 10 2 8 ns
40 td(CLKINH-H1L) Delay time, CLKIN high to H1
low§2 12 2 12¶2 14 2 10 2 10 2 8 ns
41 tsu(RESETH-H1L)
Setup time, RESET high before
H1 low and after ten H1 clock
cycles 10 9 9 7 6 5 ns
42 td(CLKINH-H3L) Delay time, CLKIN high to H3
low§2 12¶2 12 2 14 2 10 2 10 2 8 ns
43 td(CLKINH-H3H) Delay time, CLKIN high to H3
high§2 12¶2 12 2 14 2 10 2 10 2 8 ns
44 tdis(H1H-DZ) Disable time, H1 high to D (high
impedance) 15#13#13#12#11#9#ns
45 tdis(H3H-AZ) Disable time, H3 high to A (high
impedance) 10#9#9#8#7#6#ns
46 td(H3H-CONTROLH) Delay time, H3 high to control
signals high 10#9#9#8#7#6#ns
47 td(H1H-RWH) Delay time, H1 high to R/W high 10#9#9#8#7#6#ns
48 td(H1H-IACKH) Delay time, H1 high to IACK
high 10#9#9#8#7#6#ns
49 tdis(RESETL-ASYNCH)
Disable time, RESET low to
asynchronous reset signals
disabled (high impedance) 25#21#21#17#14#12#ns
†P = tc(CI)
‡Specified by design but not tested
§See Figure 22 for temperature dependence .
¶14 ns for the extended temperature ’C31-40
#This value is characterized but not tested
qmaa“
‘ \
A as M
an ) 39 *41‘40 #pM
HIjjfiWW
42*!" \ \ \ \
Hamva—v—
"—W ‘Ten H1 Clockcycles 4.1
\fiP‘F \
4—‘—&‘ 1 @
*9 TEXAS
INSTRUMENTS
POST omcg aox ~43 I HOUSTON TEXAS 7725mm
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B – MARCH 1996 – REVISED JANUARY 1999
28 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
timing parameters for RESET for the TMS320C31 and TMS320LC31 (continued)
CLKIN
H1
H3
38
39
42
45
46
49
48
41
40
43
RESET
(see Notes A and B)
IACK
Ten H1 Clock Cycles
D
(see Note C)
A
(see Note C)
Control Signals
(see Note D)
Asynchronous
Reset Signals
(see Note A)
44
47
TMS320C31 R/W
(see Note E)
NOTES: A. Asynchronous reset signals include XF0/1, CLKX0, DX0, FSX0, CLKR0, DR0, FSR0, and TCLK0/1.
B. RESET is an asynchronous input and can be asserted at any point during a clock cycle. If the specified timings are met, the exact
sequence shown occurs; otherwise, an additional delay of one clock cycle is possible.
C. In microprocessor mode, the reset vector is fetched twice, with seven software wait states each time. In microcomputer mode, the
reset vector is fetched twice, with no software wait states.
D. Control signals include STRB.
E. The R/W outputs are placed in a high-impedance state during reset and can be provided with a resistive pullup, nominally
18–22 kΩ, if undesirable spurious writes are caused when these outputs go low.
Figure 21. Timing for RESET
5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 1000
0
2
4
6
8
10
12
14
16
18
20
22
Case Temperature (°C)
CLKIN to H1 and H3 (ns)
TMS320C31-40 (Extended Temperature)
TMS320C31-40
4.75 V ≤ VDD ≤ 5.25 V
105 110 115 120 125
Extended
Temperature
Range
Figure 22. CLKIN to H1 and H3 as a Function of Temperature
*5 TEXAS
INSTRUMENTS
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B – MARCH 1996 – REVISED JANUARY 1999
29
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
interrupt response timing
The following table defines the timing parameters for the INT signals. The numbers shown in Figure 23
correspond with those in the NO. column of the table below.
timing parameters for INT3–INT0 response (see Figure 23)
NO. ’LC31-33 ’C31-40
’LC31-40 ’C31-50 ’C31-60 ’C31-80 UNIT
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
50 tsu(INT-H1L) Setup time, INT3–
INT0 before H1 low 15 13 10 8 5 ns
51 tw(INT)
Pulse duration,
interrupt to ensure
only one interrupt P 2P†‡ P2P†‡ P2P†‡ P2P†‡ P2P†‡ ns
†This value is characterized but not tested.
‡P = tc(H)
The interrupt (INT) pins are asynchronous inputs that can be asserted at any time during a clock cycle. The
TMS320C3x interrupts
are
level-sensitive, not edge-sensitive. Interrupts are detected on the falling edge of H1.
Therefore, interrupts must be set up and held to the falling edge of H1 for proper detection. The CPU and DMA
respond to detected interrupts on instruction-fetch boundaries only.
For the processor to recognize only one interrupt on a given input, an interrupt pulse must be set up and held
to:
A minimum of one H1 falling edge
No more than two H1 falling edges
The TMS320C3x can accept an interrupt from the same source every two H1 clock cycles.
If the specified timings are met, the exact sequence shown in Figure 23 occurs; otherwise, an additional delay
of one clock cycle is possible.
Flag
INT3 —INTD
ADDR
Data
INSTRUMENTS
{5" TEXAS
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B – MARCH 1996 – REVISED JANUARY 1999
30 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
timing parameters for INT3–INT0 response (continued)
Reset or
Interrupt
Vector Read
Fetch First
Instruction of
Service
Routine
H3
H1
INT3 –INT0
Pin
INT3 –INT0
Flag
ADDR
Data
Vector Address First Instruction Address
50
51
Figure 23. Timing for INT3–INT0 Response
*9 TEXAS
INSTRUMENTS
POST omcg aox ~43 I HOUSTON TEXAS 7725M»
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B – MARCH 1996 – REVISED JANUARY 1999
31
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
interrupt-acknowledge timing
The IACK output goes active on the first half-cycle (HI rising) of the decode phase of the IACK instruction and
goes inactive at the first half-cycle (HI rising) of the read phase of the IACK instruction.
The following table defines the timing parameters for the IACK signal. The numbers shown in Figure 24
correspond with those in the NO. column of the table below.
timing parameters for IACK (see Note 7 and Figure 24)
NO. ’LC31-33 ’C31-40
’LC31-40 ’C31-50 ’C31-60 ’C31-80 UNIT
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
52 td(H1H-IACKL) Delay time, H1 high to IACK
low 10 9 7 6 5 ns
53 td(H1H-IACKH) Delay time, H1 high to IACK
high 10 9 7 6 5 ns
NOTE 7: IACK goes active on the first half-cycle (H1 rising) of the decode phase of the IACK instruction and goes inactive at the first half-cycle
(H1 rising) of the read phase of the IACK instruction. Because of pipeline conflicts, IACK remains low for one cycle even if the decode
phase of the IACK instruction is extended.
H3
H1
IACK
ADDR
Data
52 53
Fetch IACK
Instruction IACK Data
Read
Decode IACK
Instruction
Figure 24. Timing for IACK
‘a H1 HVSCK
O'cte twme CLKX/Fl
Putse d"ratmn CLKX/R high/tom
Dela" tvme CLKX to DX Valvd
Setup “me DH betore CLKR tD'
HDld tvme DR tram CLKR ‘0‘“
Dela" tvme CLKX tD mtemat FSX hvgh/ln'"
Setup tvme FSH belDre CLKR ‘0‘“
HDld tvme FSX/Fl mp“! tram CLKXJR‘
Setup “me e"lemal FSX betore CLKX
ay e 1,
‘d FSXVDX V
*9 TEXAS
INSTRUMENTS
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B – MARCH 1996 – REVISED JANUARY 1999
32 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
serial-port timing parameters for TMS320C31-33 and TMS320LC31-33 (see Figure 25 and Figure 26)
NO
’LC31-33
UNIT
NO
.MIN MAX
UNIT
54 td(H1H-SCK) Delay time, H1 high to internal CLKX/R 15 ns
55
t(SCK)
Cycle time CLKX/R
CLKX/R ext tc(H)x2.6
ns
55
t
c(SCK)
C
y
cle
time
,
CLKX/R
CLKX/R int tc(H)x2 tc(H)x232
ns
56
t(SCK)
Pulse duration CLKX/R high/low
CLKX/R ext tc(H)+12
ns
56
t
w(SCK)
P
u
lse
d
u
ration
,
CLKX/R
high/lo
wCLKX/R int [tc(SCK)/2]–15 [tc(SCK)/2]+5
ns
57 tr(SCK) Rise time, CLKX/R 8 ns
58 tf(SCK) Fall time, CLKX/R 8 ns
59
td(C DX)
Delay time CLKX to DX valid
CLKX ext 35
ns
59
t
d(C-DX)
Dela
y
time
,
CLKX
to
DX
v
alid
CLKX int 20
ns
60
t(DR CLKRL)
Setu
p
time DR before CLKR low
CLKR ext 10
ns
60
t
su(DR-CLKRL)
Set
u
p
time
,
DR
before
CLKR
lo
wCLKR int 25
ns
61
th(CLKRL DR)
Hold time DR from CLKR low
CLKR ext 10
ns
61
t
h(CLKRL-DR)
Hold
time
,
DR
from
CLKR
lo
wCLKR int 0
ns
62
td(C FSX)
Delay time CLKX to internal FSX high/low
CLKX ext 32
ns
62
t
d(C-FSX)
Dela
y
time
,
CLKX
to
internal
FSX
high/lo
wCLKX int 17
ns
63
t(FSR CLKRL)
Setu
p
time FSR before CLKR low
CLKR ext 10
ns
63
t
su(FSR-CLKRL)
Set
u
p
time
,
FSR
before
CLKR
lo
wCLKR int 10
ns
64
th(SCKL FS)
Hold time FSX/R in
p
ut from CLKX/R low
CLKX/R ext 10
ns
64
t
h(SCKL-FS)
Hold
time
,
FSX/R
inp
u
t
from
CLKX/R
lo
wCLKX/R int 0
ns
65
t(FSX C)
Setu
p
time external FSX before CLKX
CLKX ext –[tc(H)–8]†[tc(SCK)/2]–10†
ns
65
t
su(FSX-C)
Set
u
p
time
,
e
x
ternal
FSX
before
CLKX
CLKX int [tc(H)–21]†tc(SCK)/2†
ns
66
td(CH DX)V
Delay time, CLKX to first DX bit, FSX CLKX ext 36†
ns
66
t
d(CH-DX)V
y, ,
precedes CLKX high CLKX int 21†
ns
67 td(FSX-DX)V Delay time, FSX to first DX bit, CLKX precedes FSX 36†ns
68 td(CH-DXZ) Delay time, CLKX high to DX high impedance following last data
bit 20†ns
†This value is characterized but not tested
td H|HVSCK
Ode time CLKXJR
P‘Wse d“ratn‘m CLKX/R mgh/mm
De‘a" hme CLKX to DX vahd
Sel‘p nme DR bemre CLKH (6'
Hum time DR lrom CLKH IO'”
De‘a" nme CLKX m mtema} FSX mthh‘r“
Sel‘p nme FSR bemre CLKH IO'“
Hu‘d nme FSX/R mpm 'rom CLKX/Fl IO'“
Sevp time eflema‘ FSX bemre CLKX
L
td FSXVDX V
*9 TEXAS
INSTRUMENTS
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B – MARCH 1996 – REVISED JANUARY 1999
33
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
serial-port timing parameters for TMS320C31-40 and TMS320LC31-40 (see Figure 25 and Figure 26)
NO.
’C31-40
’LC31-40 UNIT
MIN MAX
54 td(H1H-SCK) Delay time, H1 high to internal CLKX/R 13 ns
55
t(SCK)
Cycle time CLKX/R
CLKX/R ext tc(H)x2.6
ns
55
t
c(SCK)
C
y
cle
time
,
CLKX/R
CLKX/R int tc(H)x2 tc(H)x232
ns
56
t(SCK)
Pulse duration CLKX/R high/low
CLKX/R ext tc(H)+10
ns
56
t
w(SCK)
P
u
lse
d
u
ration
,
CLKX/R
high/lo
wCLKX/R int [tc(SCK)/2]–5 [tc(SCK)/2]+5
ns
57 tr(SCK) Rise time, CLKX/R 7 ns
58 tf(SCK) Fall time, CLKX/R 7 ns
59
td(C DX)
Delay time CLKX to DX valid
CLKX ext 30
ns
59
t
d(C-DX)
Dela
y
time
,
CLKX
to
DX
v
alid
CLKX int 17
ns
60
t(DR CLKRL)
Setu
p
time DR before CLKR low
CLKR ext 9
ns
60
t
su(DR-CLKRL)
Set
u
p
time
,
DR
before
CLKR
lo
wCLKR int 21
ns
61
th(CLKRL DR)
Hold time DR from CLKR low
CLKR ext 9
ns
61
t
h(CLKRL-DR)
Hold
time
,
DR
from
CLKR
lo
wCLKR int 0
ns
62
td(C FSX)
Delay time CLKX to internal FSX high/low
CLKX ext 27
ns
62
t
d(C-FSX)
Dela
y
time
,
CLKX
to
internal
FSX
high/lo
wCLKX int 15
ns
63
t(FSR CLKRL)
Setu
p
time FSR before CLKR low
CLKR ext 9
ns
63
t
su(FSR-CLKRL)
Set
u
p
time
,
FSR
before
CLKR
lo
wCLKR int 9
ns
64
th(SCKL FS)
Hold time FSX/R in
p
ut from CLKX/R low
CLKX/R ext 9
ns
64
t
h(SCKL-FS)
Hold
time
,
FSX/R
inp
u
t
from
CLKX/R
lo
wCLKX/R int 0
ns
65
t(FSX C)
Setu
p
time external FSX before CLKX
CLKX ext –[tc(H)–8]†[tc(SCK)/2]–10†
ns
65
t
su(FSX-C)
Set
u
p
time
,
e
x
ternal
FSX
before
CLKX
CLKX int [tc(H)–21]†tc(SCK)/2†
ns
66
td(CH DX)V
Delay time, CLKX to first DX bit, FSX CLKX ext 30†
ns
66
t
d(CH-DX)V
y, ,
precedes CLKX high CLKX int 18†
ns
67 td(FSX-DX)V Delay time, FSX to first DX bit, CLKX precedes FSX 30†ns
68 td(CH-DXZ) Delay time, CLKX high to DX high impedance following last data
bit 17† ns
†This value is characterized but not tested
‘a H1 HVSCK
O'cte twme CLKX/Fl
Putse d"ratmn CLKX/R high/tom
Dela" tvme CLKX to DX Valvd
Setup “me DH betore CLKR tD'
HDld tvme DR tram CLKR ‘0‘“
Dela" tvme CLKX tD mtemat FSX hvgh/ln'"
Setup tvme FSH belDre CLKR ‘0‘“
HDld tvme FSX/Fl mp“! tram CLKXJR‘
Setup “me e"lemal FSX betore CLKX
ay e 1,
‘d FSXVDX V
*9 TEXAS
INSTRUMENTS
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B – MARCH 1996 – REVISED JANUARY 1999
34 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
serial-port timing parameters for TMS320C31-50 (see Figure 25 and Figure 26)
NO
’C31-50
UNIT
NO
.MIN MAX
UNIT
54 td(H1H-SCK) Delay time, H1 high to internal CLKX/R 10 ns
55
t(SCK)
Cycle time CLKX/R
CLKX/R ext tc(H)x2.6
ns
55
t
c(SCK)
C
y
cle
time
,
CLKX/R
CLKX/R int tc(H)x2 tc(H)x232
ns
56
t(SCK)
Pulse duration CLKX/R high/low
CLKX/R ext tc(H)+10
ns
56
t
w(SCK)
P
u
lse
d
u
ration
,
CLKX/R
high/lo
wCLKX/R int [tc(SCK)/2]–5 [tc(SCK)/2]+5
ns
57 tr(SCK) Rise time, CLKX/R 6 ns
58 tf(SCK) Fall time, CLKX/R 6 ns
59
td(C DX)
Delay time CLKX to DX valid
CLKX ext 24
ns
59
t
d(C-DX)
Dela
y
time
,
CLKX
to
DX
v
alid
CLKX int 16
ns
60
t(DR CLKRL)
Setu
p
time DR before CLKR low
CLKR ext 9
ns
60
t
su(DR-CLKRL)
Set
u
p
time
,
DR
before
CLKR
lo
wCLKR int 17
ns
61
th(CLKRL DR)
Hold time DR from CLKR low
CLKR ext 7
ns
61
t
h(CLKRL-DR)
Hold
time
,
DR
from
CLKR
lo
wCLKR int 0
ns
62
td(C FSX)
Delay time CLKX to internal FSX high/low
CLKX ext 22
ns
62
t
d(C-FSX)
Dela
y
time
,
CLKX
to
internal
FSX
high/lo
wCLKX int 15
ns
63
t(FSR CLKRL)
Setu
p
time FSR before CLKR low
CLKR ext 7
ns
63
t
su(FSR-CLKRL)
Set
u
p
time
,
FSR
before
CLKR
lo
wCLKR int 7
ns
64
th(SCKL FS)
Hold time FSX/R in
p
ut from CLKX/R low
CLKX/R ext 7
ns
64
t
h(SCKL-FS)
Hold
time
,
FSX/R
inp
u
t
from
CLKX/R
lo
wCLKX/R int 0
ns
65
t(FSX C)
Setu
p
time external FSX before CLKX
CLKX ext –[tc(H)–8]†[tc(SCK)/2]–10†
ns
65
t
su(FSX-C)
Set
u
p
time
,
e
x
ternal
FSX
before
CLKX
CLKX int –[tc(H)–21]†tc(SCK)/2†
ns
66
td(CH DX)V
Delay time, CLKX to first DX bit, FSX CLKX ext 24†
ns
66
t
d(CH-DX)V
y, ,
precedes CLKX high CLKX int 14†
ns
67 td(FSX-DX)V Delay time, FSX to first DX bit, CLKX precedes FSX 24†ns
68 td(CH-DXZ) Delay time, CLKX high to DX high impedance following last
data bit 14†ns
†This value is characterized but not tested
td H|HVSCK
Ode time CLKXJR
P‘Wse d“ratn‘m CLKX/R mgh/mm
De‘a" hme CLKX to DX vahd
Sel p time DR bemre CLKH 10'"
Hu‘d nme DR lrom CLKH IO'“
D‘\‘ tr“ CLKX t‘ VP “3! FSX hr‘M‘
Sel‘p nme FSR bemre CLKH IO'“
Hu‘d nme FSX/R mpm 'rom CLKX/Fll
Sel p time e"1erna\ FSX bemre CLKX
De‘ay twme. CLKX to first DX be FSX
td FSXVDX V
*9 TEXAS
INSTRUMENTS
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B – MARCH 1996 – REVISED JANUARY 1999
35
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
serial-port timing parameters for TMS320C31-60 (see Figure 25 and Figure 26)
NO
’C31-60
UNIT
NO
.MIN MAX
UNIT
54 td(H1H-SCK) Delay time, H1 high to internal CLKX/R 8 ns
55
t(SCK)
Cycle time CLKX/R
CLKX/R ext tc(H)x2.6
ns
55
t
c(SCK)
C
y
cle
time
,
CLKX/R
CLKX/R int tc(H)x2 tc(H)x232
ns
56
t(SCK)
Pulse duration CLKX/R high/low
CLKX/R ext tc(H)+10
ns
56
t
w(SCK)
P
u
lse
d
u
ration
,
CLKX/R
high/lo
wCLKX/R int [tc(SCK)/2]–5 [tc(SCK)/2]+5
ns
57 tr(SCK) Rise time, CLKX/R 5 ns
58 tf(SCK) Fall time, CLKX/R 5 ns
59
td(C DX)
Delay time CLKX to DX valid
CLKX ext 20
ns
59
t
d(C-DX)
Dela
y
time
,
CLKX
to
DX
v
alid
CLKX int 15
ns
60
t(DR CLKRL)
Setu
p
time DR before CLKR low
CLKR ext 8
ns
60
t
su(DR-CLKRL)
Set
u
p
time
,
DR
before
CLKR
lo
wCLKR int 15
ns
61
th(CLKRL DR)
Hold time DR from CLKR low
CLKR ext 6
ns
61
t
h(CLKRL-DR)
Hold
time
,
DR
from
CLKR
lo
wCLKR int 0
ns
62
td(C FSX)
Delay time CLKX to internal FSX high/low
CLKX ext 20
ns
62
t
d(C-FSX)
D
e
l
ay
ti
me,
CLKX
t
o
i
n
t
erna
l
FSX
hi
g
h/l
ow CLKX int 14
ns
63
t(FSR CLKRL)
Setu
p
time FSR before CLKR low
CLKR ext 6
ns
63
t
su(FSR-CLKRL)
Set
u
p
time
,
FSR
before
CLKR
lo
wCLKR int 6
ns
64
th(SCKL FS)
Hold time FSX/R in
p
ut from CLKX/R low
CLKX/R ext 6
ns
64
t
h(SCKL-FS)
Hold
time
,
FSX/R
inp
u
t
from
CLKX/R
lo
wCLKX/R int 0
ns
65
t(FSX C)
Setu
p
time external FSX before CLKX
CLKX ext –[tc(H)–8]†[tc(SCK)/2]–10†
ns
65
t
su(FSX-C)
Set
u
p
time
,
e
x
ternal
FSX
before
CLKX
CLKX int –[tc(H)–21]†tc(SCK)/2†
ns
66
td(CH DX)V
Dela
y
time
,
CLKX to first DX bit
,
FSX CLKX ext 20†
ns
66
t
d(CH-DX)V
Delay
time,
CLKX
to
first
DX
bit,
FSX
precedes CLKX high CLKX int 12†
ns
67 td(FSX-DX)V Delay time, FSX to first DX bit, CLKX precedes FSX 20†ns
68 td(CH-DXZ) Delay time, CLKX high to DX high impedance following last
data bit 12†ns
†This value is characterized but not tested
‘a H1 HVSCK
O'cte twme CLKX/Fl
Putse d"ratmn CLKX/R high/tom
Dela" tvme CLKX to DX Valvd
Setup “me DH betore CLKR tD'
HDld tvme DR tram CLKR ‘0‘“
Dela" tvme CLKX tD mtemat FSX hvgh/ln'"
Setup tvme FSH belDre CLKR ‘0‘“
HDld tvme FSX/Fl mp“! tram CLKXJR‘
Setup “me e"lemal FSX betore CLKX
ay e 1,
‘d FSXVDX V
*9 TEXAS
INSTRUMENTS
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B – MARCH 1996 – REVISED JANUARY 1999
36 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
serial-port timing parameters for TMS320C31-80 (see Figure 25 and Figure 26)
NO
’C31-80
UNIT
NO
.MIN MAX
UNIT
54 td(H1H-SCK) Delay time, H1 high to internal CLKX/R 7 ns
55
t(SCK)
Cycle time CLKX/R
CLKX/R ext tc(H)x2.6
ns
55
t
c(SCK)
C
y
cle
time
,
CLKX/R
CLKX/R int tc(H)x2 tc(H)x232
ns
56
t(SCK)
Pulse duration CLKX/R high/low
CLKX/R ext tc(H)+6
ns
56
t
w(SCK)
P
u
lse
d
u
ration
,
CLKX/R
high/lo
wCLKX/R int [tc(SCK)/2]–5 [tc(SCK)/2]+5
ns
57 tr(SCK) Rise time, CLKX/R 3 ns
58 tf(SCK) Fall time, CLKX/R 3 ns
59
td(C DX)
Delay time CLKX to DX valid
CLKX ext 16
ns
59
t
d(C-DX)
Dela
y
time
,
CLKX
to
DX
v
alid
CLKX int 11
ns
60
t(DR CLKRL)
Setu
p
time DR before CLKR low
CLKR ext 6
ns
60
t
su(DR-CLKRL)
Set
u
p
time
,
DR
before
CLKR
lo
wCLKR int 13
ns
61
th(CLKRL DR)
Hold time DR from CLKR low
CLKR ext 5
ns
61
t
h(CLKRL-DR)
Hold
time
,
DR
from
CLKR
lo
wCLKR int 0
ns
62
td(C FSX)
Delay time CLKX to internal FSX high/low
CLKX ext 16
ns
62
t
d(C-FSX)
Dela
y
time
,
CLKX
to
internal
FSX
high/lo
wCLKX int 12
ns
63
t(FSR CLKRL)
Setu
p
time FSR before CLKR low
CLKR ext 5
ns
63
t
su(FSR-CLKRL)
Set
u
p
time
,
FSR
before
CLKR
lo
wCLKR int 5
ns
64
th(SCKL FS)
Hold time FSX/R in
p
ut from CLKX/R low
CLKX/R ext 5
ns
64
t
h(SCKL-FS)
Hold
time
,
FSX/R
inp
u
t
from
CLKX/R
lo
wCLKX/R int 0
ns
65
t(FSX C)
Setu
p
time external FSX before CLKX
CLKX ext –[tc(H)–8]†[tc(SCK)/2]–10†
ns
65
t
su(FSX-C)
Set
u
p
time
,
e
x
ternal
FSX
before
CLKX
CLKX int –[tc(H)–21]†tc(SCK)/2†
ns
66
td(CH DX)V
Delay time, CLKX to first DX bit, FSX CLKX ext 16
ns
66
t
d(CH-DX)V
y, ,
precedes CLKX high CLKX int 10
ns
67 td(FSX-DX)V Delay time, FSX to first DX bit, CLKX precedes FSX 16 ns
68 td(CH-DXZ) Delay time, CLKX high to DX high impedance following last data
bit 10 ns
†This value is characterized but not tested
scription of s
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*9 TEXAS
INSTRUMENTS
POST omcg sex was I HOUSTON TEXAS 7725mm
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B – MARCH 1996 – REVISED JANUARY 1999
37
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
data-rate timing modes
Unless otherwise indicated, the data-rate timings shown in Figure 25 and Figure 26 are valid for all serial-port
modes, including handshake. For a functional description of serial-port operation refer to subsection 8.2.12 of
the
TMS320C3x User’s Guide
(literature number SPRU031).
The serial-port timing parameters for seven ’C3x devices are defined in the preceding “serial-port timing
parameters” tables (such as “serial-port timing parameters for TMS320C31-60”). The numbers shown in
Figure 25 and Figure 26 correspond with those in the NO. column of each table.
FSX(EXT)
FSX(INT)
FSR
DR
DX
CLKX/R
H1
61
57 58
55
56
56
60
65 64
62
64
63
62
66
54
54
68
Bit 0
Bit
n-1
Bit
n-2
Bit
n-1
Bit
n-2
59
NOTES: A. Timing diagrams show operations with CLKXP = CLKRP = FSXP = FSRP = 0.
B. Timing diagrams depend on the length of the serial-port word, where n = 8, 16, 24, or 32 bits, respectively.
Figure 25. Timing for Fixed Data-Rate Mode
fl TEXAS
INSTRUMENTS
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B – MARCH 1996 – REVISED JANUARY 1999
38 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
data-rate timing modes (continued)
CLKX/R
FSX(INT)
FSX(EXT)
DX
FSR
DR
62
65
64
63
60 61
59 68
67
66 Bit 0
Bit
n-2
Bit
n-3
Bit
n-2
Bit
n-3
Bit
n-1
Bit
n-1
NOTES: A. Timing diagrams show operation with CLKXP = CLKRP = FSXP = FSRP = 0.
B. Timing diagrams depend on the length of the serial-port word, where n = 8, 16, 24, or 32 bits, respectively.
C. The timings that are not specified expressly for the variable data-rate mode are the same as those that are specified for the fixed
data-rate mode.
Figure 26. Timing for Variable Data-Rate Mode
svxal fil‘
SlNEIWnHlSN]
tsu HOLDVHTL
tv H|LVHOLDA
tw HOLD
tw HOLDA
td H1 LVSH H
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B - MARCH 1996 - REVISED JANUARY 1999
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
•39
HOLD timing
HOLD is an asynchronous input that can be asserted at any time during a clock cycle. If the specified timings are met, the exact sequence
shown in Figure 27 occurs; otherwise, an additional delay of one clock cycle is possible.
The table, “timing parameters for HOLD/HOLDA”, defines the timing parameters for the HOLD and HOLDA signals. The numbers shown in
Figure 27 correspond with those in the NO. column of the table.
The NOHOLD bit of the primary-bus control register overrides the HOLD signal. When this bit is set, the device comes out of hold and prevents
future hold cycles.
Asserting HOLD prevents the processor from accessing the primary bus. Program execution continues until a read from or a write to the
primary bus is requested. In certain circumstances, the first write is pending, thus allowing the processor to continue until a second write is
encountered.
timing parameters for HOLD/HOLDA (see Figure 27)
NO. ’LC31-33 ’C31-40
’LC31-40 ’C31-50 ’C31-60 ’C31-80 UNIT
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
69 tsu(HOLD-H1L) Setup time, HOLD before H1 low 15 13 10 8 5 ns
70 tv(H1L-HOLDA) Valid time, HOLDA after H1 low 0†10 0†9 0†7 0†6 0†5 ns
71 tw(HOLD)‡Pulse duration, HOLD low 2tc(H) 2tc(H) 2tc(H) 2tc(H) 2tc(H) ns
72 tw(HOLDA) Pulse duration, HOLDA low tcH–5†tcH–5†tcH–5†tcH–5†tcH–5†ns
73 td(H1L-SH)H Delay time, H1 low to STRB high for a HOLD 0§10 0§9 0§7 0§6 0§4 ns
74 tdis(H1L-S) Disable time, H1 low to STRB to the
high-impedance state 0§10†0§9†0§8†0§7†0§7†ns
75 ten(H1L-S) Enable time, H1 low to STRB enabled (active) 0§10 0§9 0§7 0§6 0§6 ns
76 tdis(H1L-RW) Disable time, H1 low to R/W to the
high-impedance state 0†10†0†9†0†8†0†7†0†6†ns
77 ten(H1L-RW) Enable time, H1 low to R/W enabled (active) 0†10 0†9 0†7 0†6 0†6 ns
78 tdis(H1L-A) Disable time, H1 low to address to the
high-impedance state 0§10†0§10†0§8†0§7†0§7†ns
79 ten(H1L-A) Enable time, H1 low to address enabled (valid) 0§15 0§13 0§12 0§11 0§10 ns
80 tdis(H1H-D) Disable time, H1 high to data to the
high-impedance state 0§10†0§9†0§8†0§7†0§6†ns
†This value is characterized but not tested
‡HOLD is an asynchronous input and can be asserted at any point during a clock cycle. If the specified timings are met, the exact sequence shown in Figure 27 occurs; otherwise,
an additional delay of one clock cycle is possible.
§Not tested
\
/
_/
_\/\1\/\/\
*k
HP
{5" TEXAS
Wlile Dali
INSTRUMENTS
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B – MARCH 1996 – REVISED JANUARY 1999
40 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
HOLD timing (continued)
H3
H1
HOLD
HOLDA
STRB
R/W
A
D
69 69
70
71
70
72
74
76
75
77
79
78
80
73
Write Data
NOTE A: HOLDA goes low in response to HOLD going low and continues to remain low until one H1 cycle
after HOLD goes back high.
Figure 27. Timing for HOLD/HOLDA
/_\/_\/_\/+\/+\/_\
/ 1\ JMJ /\_
4w
T“ w A“ x
)C TX )—**—I X
*9 TEXAS
INSTRUMENTS
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B – MARCH 1996 – REVISED JANUARY 1999
41
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
general-purpose I/O timing
Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLK0/1. The contents of the internal
control registers associated with each peripheral define the modes for these pins.
peripheral pin I/O timing
The table, timing parameters for peripheral pin general-purpose I/O, defines peripheral pin general-purpose I/O
timing parameters. The numbers shown in Figure 28 correspond with those in the NO. column of the table
below.
timing parameters for peripheral pin general-purpose I/O (see Note 8 and Figure 28)
NO. LC31-33 ’C31-40
’LC31-40 ’C31-50 ’C31-60 ’C31-80 UNIT
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
81 tsu(GPIO-H1L)
Setup time,
general-purpose input
before H1 low 12 10 9 8 7 ns
82 th(H1L-GPIO)
Hold time,
general-purpose input
after H1 low 0 0 0 0 0 ns
83 td(H1H-GPIO)
Delay time,
general-purpose output
after H1 high 15 13 10 8 6 ns
NOTE 8: Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLK0/1. The modes of these pins are defined by the contents
of internal-control registers associated with each peripheral.
Peripheral
Pin
(see Note A)
H1
H3
83 83
81 82
NOTE A: Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLK0/1.
Figure 28. Timing for Peripheral Pin General-Purpose I/O
'o'o‘wo
fifotofotofofotofotofotofofotofo
Sampled
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B – MARCH 1996 – REVISED JANUARY 1999
42 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
changing the peripheral pin I/O modes
The following tables show the timing parameters for changing the peripheral pin from a general-purpose output
pin to a general-purpose input pin and vice versa. The numbers shown in Figure 29 and Figure 30 correspond
to those shown in the NO. column of the tables below.
timing parameters for peripheral pin changing from general-purpose output to input mode
(see Note 8 and Figure 29)
NO. ’LC31-33 ’C31-40
’LC31-40 ’C31-50 ’C31-60 ’C31-80 UNIT
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
84 th(H1H) Hold time, peripheral pin after
H1 high 15 13 10 8 6 ns
85 tsu(GPIO-H1L) Setup time, peripheral pin
before H1 low 10 9 9 8 7 ns
86 th(H1L-GPIO) Hold time, peripheral pin after
H1 low 0 0 0 0 0 ns
NOTE 8: Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLK0/1. The modes of these pins are defined by the contents
of internal-control registers associated with each peripheral.
86
85
84
Value on Pin
Seen in
Peripheral-
Control
Register
Synchronizer Delay
Buffers Go
From
Output to
Input
Execution
of Store of
Peripheral-
Control
Register
Data Bit
Peripheral
Pin
(see Note A)
I/O
Control Bit
H1
H3
Output
Data
Seen
Data
Sampled
NOTE A: Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLK0/1.
Figure 29. Timing for Change of Peripheral Pin From General-Purpose Output to Input Mode
H3
HI
I/O
Conlrol
Bil
Peripheral
Pin
(see Note A)
J
j
*9 TEXAS
INSTRUMENTS
POST omcg aox ~43 I HOUSTON TEXAS 7725mm
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B – MARCH 1996 – REVISED JANUARY 1999
43
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
timing parameters for peripheral pin changing from general-purpose input to output mode
(see Note 8 and Figure 30)
NO. ’LC31-33 ’C31-40
’LC31-40 ’C31-50 ’C31-60 ’C31-80 UNIT
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
87 td(H1H-GPIO)
Delay time, H1 high to
peripheral pin switching
from input to output 15 13 10 8 6 ns
NOTE 8: Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLK0/1. The modes of these pins are defined by the contents
of internal-control registers associated with each peripheral.
Peripheral
Pin
(see Note A)
I/O
Control
Bit
H1
H3
Execution of Store
of Peripheral-
Control Register
87
NOTE A: Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLK0/1.
Figure 30. Timing for Change of Peripheral Pin From General-Purpose Input to Output Mode
tsu TCLKVH|L
th H|L7TCLK
td H|H7TCLK
t —** *' C“c\etvme TCLK
P "Se d' ram)" TCLK mgh/m'“
svxal {I}
DESCRIPTION:
SLNHWHHLSNI
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B - MARCH 1996 - REVISED JANUARY 1999
44 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
•
timer pin timing
Valid logic-level periods and polarity are specified by the contents of the internal control registers.
The following tables define the timing parameters for the timer pin. The numbers shown in Figure 31 correspond with those in the NO. column
of the tables below.
timing parameters for timer pin for TMS320LC31-33 (see Figure 31) †
NO. DESCRIPTION
‡
’LC31-33 ’C31-40,
’LC31-40 UNIT
MIN MAX MIN MAX
88 tsu(TCLK-H1L) Setup time, TCLK external before H1 low 12 10 ns
89 th(H1L-TCLK) Hold time, TCLK external after H1 low 0 0 ns
90 td(H1H-TCLK) Delay time, H1 high to TCLK internal valid 10 9 ns
91
t(TCLK)
Cycle time TCLK
TCLK ext tc(H)×2.6 tc(H)×2.6
ns
91
t
c(TCLK)
C
y
cle
time
,
TCLK
TCLK int tc(H)×2 tc(H)×232‡tc(H)×2 tc(H)×232‡
ns
92
t(TCLK)
Pulse duration TCLK high/low
TCLK ext tc(H)+12 tc(H)+10
ns
92
t
w(TCLK)
P
u
lse
d
u
ration
,
TCLK
high/lo
wTCLK int [tc(TCLK)/2]–15 [tc(TCLK)/2]+5 [tc(TCLK)/2]–5 [tc(TCLK)/2]+5
ns
†Timing parameters 88 and 89 are applicable for a synchronous input clock. Timing parameters 91 and 92 are applicable for an asynchronous input clock.
‡Specified by design but not tested
timing parameters for timer pin for TMS320LC31-40, TMS320C31-50, and TMS320C31-60 (see Figure 31) †
NO
DESCRIPTION‡
’C31-50 ’C31-60 ’C31-80
UNIT
NO
.
DESCRIPTION‡
MIN MAX MIN MAX MIN MAX
UNIT
88 tsu(TCLK-H1L) Setup time, TCLK external
before H1 low 8 6 5 ns
89 th(H1L-TCLK) Hold time, TCLK external
after H1 low 0 0 0 ns
90 td(H1H-TCLK) Delay time, H1 high to TCLK
internal valid 9 8 6 ns
91
t(TCLK)
TCLK ext tc(H)×2.6 tc(H)×2.6 tc(H)×2.6
ns
91
t
c(TCLK) TCLK int tc(H)×2 tc(H)×232‡tc(H)×2 tc(H)×232‡tc(H)×2 tc(H)×232‡
ns
92
t(TCLK)
TCLK ext tc(H)+10 tc(H)+10 tc(H)+6
ns
92
t
w(TCLK) TCLK int [tc(TCLK)/2]–5 [tc(TCLK)/2]+5 [tc(TCLK)/2]–5 [tc(TCLK)/2]+5 [tc(TCLK)/2]–5 [tc(TCLK)/2]+5
ns
†Timing parameters 88 and 89 are applicable for a synchronous input clock. Timing parameters 91 and 92 are applicable for an asynchronous input clock.
‡Specified by design but not tested
*9 TEXAS
INSTRUMENTS
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B – MARCH 1996 – REVISED JANUARY 1999
45
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
timer pin timing (continued)
90
90
89
Peripheral
Pin
(see Note A)
H1
H3
88
91 92
NOTE A: HOLDA goes low in response to HOLD going low and continues to remain low until one H1 cycle
after HOLD goes back high.
Figure 31. Timing for Timer Pin
SHZ pin timing
The following table defines the timing parameter for the SHZ pin. The number shown in Figure 32 corresponds
with that in the NO. column of the table below.
timing parameters for SHZ (see Figure 32)
NO.
’C31
’LC31 UNIT
MIN MAX
93 tdis(SHZ) Disable time, SHZ low to all O, I/O pins disabled (high impedance) 0†2P†‡ ns
†This value is characterized but not tested
‡P = tc(CI)
93
H3
H1
SHZ
All I/O Pins
NOTE A: Enabling SHZ destroys TMS320C3x register and memory contents.
Assert SHZ = 1 and reset the TMS320C3x to restore it to a known
condition.
Figure 32. Timing for SHZ
*9 TEXAS
INSTRUMENTS
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B – MARCH 1996 – REVISED JANUARY 1999
46 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SHZ pin timing (continued)
Table 1. Thermal Resistance Characteristics
PARAMETER °C/W AIR FLOW
LFPM
RθJC†11.0 N/A
RθJA‡49.0 0
RθJA‡35.5 200
RθJA‡28.0 400
RθJA‡23.5 600
RθJA‡21.6 800
RθJA‡20.0 1000
†RΘSC = junction-to-case
‡RΘJA = junction-to-free air
"D3" SO
38
"D1" SQ
”D" SQ
"D2" SQ
A
A
64
MWH
E 700121030)
0.000 (0.20)
0.010 (0.25)3
Sealing Plane
7 0.130 (4.57) MAX E—
LEADS
DIM 100 132
"D" MAX 009012201) 100012769)
MW 007012210) 1.070127.10)
"m“ MAX 0766 (19.40) 006012454)
MW 073411304) 003412372)
"D2“ MAX 001212110) 1.11212025)
MW 005512250) 1.000127.64)
"D3" NOM 000011524) 000012032)
*9 TEXAS
INSTRUMENTS
p007 omcg 00x mg I HOUSTON TEXAS 7725171 on
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B – MARCH 1996 – REVISED JANUARY 1999
47
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
MECHANICAL DATA
PQ (S-PQFP-G***) PLASTIC QUAD FLATPACK
100 LEAD SHOWN
88
0.012 (0,30)
0.008 (0,20)
64
0.025 (0,635)
Seating Plane
132
1.090 (27,69)
1.070 (27,18)
0.966 (24,54)
0.934 (23,72)
1.112 (28,25)
1.088 (27,64)
0.800 (20,32)
4040045/C 11/95
100113
6339
”D2” SQ
”D1” SQ
”D” SQ
14
”D3” SQ
38
DIM
”D”
”D2”
”D3”
”D1”
NOM
MIN
MAX
MIN
MAX
MIN
MAX
LEADS ***
0.180 (4,57) MAX
100
0.890 (22,61)
0.870 (22,10)
0.766 (19,46)
0.734 (18,64)
0.912 (23,16)
0.888 (22,56)
0.600 (15,24)
0.004 (0,10)
M
0.006 (0,15)
0.010 (0,25)
0.020 (0,51) MIN
0.130 (3,30)
0.150 (3,81)
0.006 (0,16) NOM
Gage Plane
0.036 (0,91)
0.046 (1,17)
0°–8°
89
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MO-069
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Copyright 1999, Texas Instruments Incorporated
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