TMS320C206 datasheet - Digital Signal Processors

Details, datasheet, quote on part number: TMS320C206
PartTMS320C206
CategorySemiconductors => Processors => Other Processors
Part familyTMS320C206 Digital Signal Processor
TitleTMS320 Family
DescriptionDigital Signal Processor 100-LQFP
CompanyTexas Instruments, Inc.
ROHSY
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  Mecanical Data
Pin nbPackage typeInd stdJEDEC codePackage qtyCarrierDevice markWidth (mm)Length (mm)Thick (mm)Pitch (mm)
100PZLQFPS-PQFP-GTMS320C206PZ 14141.4.5

 

Features, Applications

High-Performance Static CMOS Technology Includes the '320C2xLP Core CPU TMS320C206, TMS320LC206 are Members of the 'C20x/'C2000 Platform Which Also Includes the TMS320C203/LC203 and TMS320F206 Devices Instruction-Cycle Time 3.3 V Source Code Compatible With TMS320C25 and other '20x Devices Upwardly Code-Compatible With TMS320C5x Devices Four External Interrupts TMS320C206, 5-V I/O (3.3-V core) TMS320LC206, 3.3-V core and I/O TMS320C206, TMS320LC206 Integrated Memory: Words of On-Chip Dual-Access Data RAM � 16 Words of On-Chip ROM � 16 Words of On-Chip Single-Access Program/ Data RAM � 16-Bit Maximum Addressable External Memory Space � 64K Program � 64K Data � 64K Input/Output (I/O) � 32K Global

32-Bit Arithmetic Logic Unit (ALU ) Accumulator � 16-Bit Multiplier With a 32-Bit Product Block Moves from Data and Program Space TMS320C206, TMS320LC206 Peripherals: � On-Chip 20-Bit Timer � On-Chip Software-Programmable Wait-State to 7) Generator � On-Chip Oscillator � On-Chip Phase-Locked Loop (PLL) � Six General-Purpose I/O Pins � Full-Duplex Asynchronous Serial Port (UART) � Enhanced Synchronous Serial Port (ESSP) With Four-Level-Deep FIFOs Input Clock Options � Options: Multiply-by-One, -Two, or -Four, and Divide-by-Two and 2) Support of Hardware Wait States Power Down IDLE Mode IEEE 1149.1-Compatible Scan-Based Emulation 100-Pin PZ Package, Small Thin Quad Flat Package (TQFP) Industrial Temperature Version Planned, to 85�C)

description

The Texas Instruments (TITM) TMS320C206 and TMS320LC206 digital signal processors (DSPs) are fabricated with static CMOS integrated-circuit technology. The architectural design is based upon that of the TMS320C20x series and is optimized for low-power operation. The combination of advanced Harvard architecture, on-chip peripherals, on-chip memory, and a highly specialized instruction set is the basis of the operational flexibility and speed of the 'C206. The 'C206 offers these advantages:

Enhanced TMS320 architectural design for increased performance and versatility Advanced integrated-circuit processing technology for increased performance 'C206 devices are pin- and code-compatible with 'C203 and 'F206 devices. Source code for the 'C206 DSPs is software-compatible with the 'C1x and 'C2x DSPs and is upwardly compatible with fifth-generation DSPs ('C5x) New static-design techniques for minimizing power consumption and increasing radiation tolerance

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. IEEE Standard - 1990, IEEE Standard Test-Access Port Device numbers are hereafter referred to in the data sheet as 'C206, unless otherwise specified. is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

VDD5 pins and 91 represent I/O supply voltage. PZ PACKAGE ( TOP VIEW )

Table 1 shows the capacity of on-chip RAM and ROM, the number of serial and parallel I/O ports, the execution time of one machine cycle, and the type of package with total pin count of the TMS320C206 and TMS320LC206 devices. Table 1. Characteristics of the TMS320C206 and TMS320LC206 Processors

ON-CHIP MEMORY (16-BIT WORDS) 'x206 DEVICES DATA TMS320C206 288 RAM DATA/ PROG + 256 ROM PROG 32K FLASH EEPROM PROG � I/O PORTS POWER SUPPLY (V) 5 (3.3 core) CYCLE TIME (ns) 25 PACKAGE TYPE WITH PIN COUNT 100-pin TQFP

25 100-pin TQFP On-chip RAM space B1 (256 words) and B2 (32 words) can be used as data memory only. On-chip RAM space B0 (256 words) can be used either in data space or program space depending on the value of the CNF bit in the ST1 register. On-chip SARAM (4K) can be mapped in program space, data space, or both.


 

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