PCF8575C Datasheet by Texas Instruments

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V'.‘ 3!. B X E I TEXAS INSTRUMENTS

PCF8575C

I2C or SMBus Master

(e.g. Processor) Peripheral Devices

RESET, ENABLE,

or control inputs

INT or status

outputs

LEDs

SDA

SCL

INT

GND

VCC

P00

P01

P02

P03

P04

P05

P06

P07

Peripheral Devices

RESET, ENABLE,

or control inputs

INT or status

outputs

LEDs

P10

P11

P12

P13

P14

P15

P16

P17

Product

Folder

Sample &

Buy

Technical

Documents

Tools &

Software

Support &

Community

PCF8575C

SCPS123F –MARCH 2005–REVISED JANUARY 2015

PCF8575C Remote 16-Bit I

C AND SMBus Low-Power I/O Expander

with Interrupt Output

1 Features 3 Description

This 16-bit I/O expander for the two-line bidirectional

1• I2C to Parallel-Port Expander bus (I2C) is designed for 4.5-V to 5.5-V VCC

• Open-Drain Interrupt Output operation.

• Low Standby-Current Consumption of The PCF8575C provides general-purpose remote I/O

10 μA Maximum expansion for most microcontroller families via the I2C

• Compatible With Most Microcontrollers interface serial clock (SCL) and serial data (SDA).

• 400-kHz Fast I2C Bus The device features a 16-bit quasi-bidirectional

• Address by Three Hardware Address Pins for Use input/output (I/O) port (P07–P00, P17–P10), including

of up to Eight Devices latched outputs with high-current drive capability for

directly driving LEDs. Each quasi-bidirectional I/O can

• Latched Outputs With High-Current Drive be used as an input or output without the use of a

Capability for Directly Driving LEDs data-direction control signal. At power on, the I/Os

• Latch-Up Performance Exceeds 100 mA Per are in 3-state mode. The strong pullup to VCC allows

JESD 78, Class II fast-rising edges into heavily loaded outputs. This

• ESD Protection Exceeds JESD 22 device turns on when an output is written high and is

switched off by the negative edge of SCL. The I/Os

– 2000-V Human-Body Model should be high before being used as inputs. After

– 200-V Machine Model power on, as all the I/Os are set to 3-state, all of them

– 1000-V Charged-Device Model can be used as inputs. Any change in setting of the

I/Os as either inputs or outputs can be done with the

2 Applications write mode. If a high is applied externally to an I/O

that has been written earlier to low, a large current

• Telecom Shelters: Filter Units (IOL) flows to GND.

• Servers Device Information(1)

• Routers (Telecom Switching Equipment)

PART NUMBER PACKAGE (PIN) BODY SIZE

• Personal Computers

SSOP (24) 8.20 mm × 5.30 mm

• Personal Electronics QSOP (24) 8.65 mm × 3.90

• Industrial Automation TVSOP (24) 5.00 mm × 4.50 mm

• Products with GPIO-Limited Processors PCF8575C SOIC (24) 15.40 mm × 7.50 mm

TSSOP (24) 7.80 mm × 4.40 mm

QFN (24) 4.0 mm × 4.0 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

l TEXAS INSTRUMENTS

PCF8575C

SCPS123F –MARCH 2005–REVISED JANUARY 2015

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Table of Contents

8.2 Functional Block Diagram....................................... 12

1 Features.................................................................. 18.3 Feature Description................................................. 13

2 Applications ........................................................... 18.4 Device Functional Modes........................................ 15

3 Description ............................................................. 19 Application and Implementation ........................ 17

4 Revision History..................................................... 29.1 Application Information............................................ 17

5 Pin Configuration................................................... 39.2 Typical Application ................................................. 17

6 Specifications......................................................... 410 Power Supply Recommendations ..................... 20

6.1 Absolute Maximum Ratings ..................................... 410.1 Power-On Reset Requirements ........................... 20

6.2 ESD Ratings.............................................................. 411 Layout................................................................... 22

6.3 Recommended Operating Conditions...................... 411.1 Layout Guidelines ................................................. 22

6.4 Thermal Information.................................................. 411.2 Layout Example .................................................... 23

6.5 Electrical Characteristics.......................................... 512 Device and Documentation Support ................. 24

6.6 I2C Interface Timing Requirements.......................... 512.1 Trademarks........................................................... 24

6.7 Switching Characteristics......................................... 612.2 Electrostatic Discharge Caution............................ 24

6.8 Typical Characteristics.............................................. 612.3 Glossary................................................................ 24

7 Parameter Measurement Information .................. 813 Mechanical, Packaging, and Orderable

8 Detailed Description............................................ 11 Information ........................................................... 24

8.1 Overview ................................................................. 11

4 Revision History

Changes from Revision E (October 2007) to Revision F Page

• Added Applications,Device Information table, Pin Functions table, ESD Ratings table, Thermal Information table,

Typical Characteristics,Feature Description section, Device Functional Modes,Application and Implementation

section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and

Mechanical, Packaging, and Orderable Information section.................................................................................................. 1

• Deleted Ordering Information table. ....................................................................................................................................... 1

Product Folder Links: PCF8575C

{L} TEXAS INSTRUMENTS

DB, DBQ, DGV, DW, OR PW PACKAGE

(TOP VIEW)

INT

P00

P01

P02

P03

P04

P05

P06

P07

GND

VCC

SDA

SCL

P17

P16

P15

P14

P13

P12

P11

P10

24 23 22 21 20

7 8 9 10 11

RGE PACKAGE

(TOP VIEW)

INT

P10

P11 SDA

P06

P07

GND

VCC

SCL

P12

P00

P01

P03

P04

P05

P17

P16

P15

P14

P13

PCF8575C

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SCPS123F –MARCH 2005–REVISED JANUARY 2015

5 Pin Configuration

Pin Functions

PIN TYPE

NAME NO. DESCRIPTION

DB, DBQ, DGV, RGE

DW, AND PW

INT 1 22 I Interrupt output. Connect to VCC through a pullup resistor.

A1 2 23 I Address input 1. Connect directly to VCC or ground. Pullup resistors are not needed.

A2 3 24 I Address input 2. Connect directly to VCC or ground. Pullup resistors are not needed.

P00 4 1 I/O P-port input/output. Open-drain design structure. Connect to VCC through a pullup resistor.

P01 5 2 I/O P-port input/output. Open-drain design structure. Connect to VCC through a pullup resistor.

P02 6 3 I/O P-port input/output. Open-drain design structure. Connect to VCC through a pullup resistor.

P03 7 4 I/O P-port input/output. Open-drain design structure. Connect to VCC through a pullup resistor.

P04 8 5 I/O P-port input/output. Open-drain design structure. Connect to VCC through a pullup resistor.

P05 9 6 I/O P-port input/output. Open-drain design structure. Connect to VCC through a pullup resistor.

P06 10 7 I/O P-port input/output. Open-drain design structure. Connect to VCC through a pullup resistor.

P07 11 8 I/O P-port input/output. Open-drain design structure. Connect to VCC through a pullup resistor.

GND 12 9 — Ground

P10 13 10 I/O P-port input/output. Open-drain design structure. Connect to VCC through a pullup resistor.

P11 14 11 I/O P-port input/output. Open-drain design structure. Connect to VCC through a pullup resistor.

P12 15 12 I/O P-port input/output. Open-drain design structure. Connect to VCC through a pullup resistor.

P13 16 13 I/O P-port input/output. Open-drain design structure. Connect to VCC through a pullup resistor.

P14 17 14 I/O P-port input/output. Open-drain design structure. Connect to VCC through a pullup resistor.

P15 18 15 I/O P-port input/output. Open-drain design structure. Connect to VCC through a pullup resistor.

P16 19 16 I/O P-port input/output. Open-drain design structure. Connect to VCC through a pullup resistor.

P17 20 17 I/O P-port input/output. Open-drain design structure. Connect to VCC through a pullup resistor.

A0 21 18 I Address input 0. Connect directly to VCC or ground. Pullup resistors are not needed.

SCL 22 19 I Serial clock line. Connect to VCC through a pullup resistor

SDA 23 20 I/O Serial data line. Connect to VCC through a pullup resistor.

VCC 24 21 — Supply voltage

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)

MIN MAX UNIT

VCC Supply voltage range –0.5 6.5 V

VIInput voltage range(2) –0.5 VCC + 0.5 V

VOOutput voltage range(2) –0.5 VCC + 0.5 V

IIK Input clamp current VI< 0 –20 mA

IOK Output clamp current VO< 0 –20 mA

IOK Input/output clamp current VO< 0 or VO> VCC ±400 μA

IOL Continuous output low current VO= 0 to VCC 50 mA

IOH Continuous output high current VO= 0 to VCC –4 mA

Continuous current through VCC or GND ±100 mA

Tstg Storage temperature range –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.

6.2 ESD Ratings

VALUE UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins 2000

V(ESD) Electrostatic discharge V

Charged device model (CDM), per JEDEC specification JESD22- 1000

C101, all pins

6.3 Recommended Operating Conditions

MIN MAX UNIT

VCC Supply voltage 4.5 5.5 V

A0, A1, A2, SDA, and SCL 0.7 × VCC VCC + 0.5

VIH High-level input voltage V

P07–P00 and P17–P10 0.8 × VCC VCC + 0.5

A0, A1, A2, SDA, and SCL –0.5 0.3 × VCC

VIL Low-level input voltage V

P07–P00 and P17–P10 –0.5 0.6 × VCC

IOHT P-port transient pullup current –10 mA

IOL P-port low-level output current 25 mA

TAOperating free-air temperature –40 85 °C

6.4 Thermal Information

PCF8575

THERMAL METRIC(1) DB DBQ DGV DW PW RGE UNIT

24 PINS

RθJA Junction-to-ambient thermal resistance 63 61 86 46 88 53 °C/W

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953).

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SCPS123F –MARCH 2005–REVISED JANUARY 2015

6.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS VCC MIN TYP(1) MAX UNIT

4.5 V to

VIK Input diode clamp voltage II= –18 mA –1.2 V

5.5 V

VPOR Power-on reset voltage(2) VI= VCC or GND, IO= 0 VPOR 1.2 1.8 V

IOHT P-port transient pullup current High during ACK VOH = GND 4.5 V –0.5 –1 mA

4.5 V to

SDA VOL = 0.4 V 3

5.5 V

VOL = 0.4 V 5 15

4.5 V to

IOL P port mA

5.5 V

VOL = 1 V 10 25

4.5 V to

INT VOL = 0.4 V 1.6

5.5 V

SCL, SDA ±2

4.5 V to

IIVI= VCC or GND μA

5.5 V

A0, A1, A2 ±1

4.5 V to

IIHL P port VI≥VCC or VI≤GND ±400 μA

5.5 V

Operating mode VI= VCC or GND, IO= 0, fSCL = 400 kHz 100 200

ICC 5.5 V μA

Standby mode VI= VCC or GND, IO= 0, fSCL = 0 kHz 2.5 10

One input at VCC – 0.6 V, 4.5 V to

ΔICC Supply current increase 200 μA

Other inputs at VCC or GND 5.5 V

4.5 V to

CiSCL VI= VCC or GND 3 7 pF

5.5 V

SDA 3 7

4.5 V to

Cio VIO = VCC or GND pF

5.5 V

P port 4 10

(1) All typical values are at VCC = 5 V, TA= 25°C.

(2) The power-on reset circuit resets the I2C bus logic with VCC < VPOR and sets all I/Os to logic high (with current source to VCC).

6.6 I2C Interface Timing Requirements

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 7)

MIN MAX UNIT

fscl I2C clock frequency 400 kHz

tsch I2C clock high time 0.6 μs

tscl I2C clock low time 1.3 μs

tsp I2C spike time 50 ns

tsds I2C serial-data setup time 100 ns

tsdh I2C serial-data hold time 0 ns

ticr I2C input rise time 20 + 0.1Cb(1) 300 ns

ticf I2C input fall time 20 + 0.1Cb(1) 300 ns

tocf I2C output fall time (10-pF to 400-pF bus) 300 ns

tbuf I2C bus free time between stop and start 1.3 μs

tsts I2C start or repeated start condition setup 0.6 μs

tsth I2C start or repeated start condition hold 0.6 μs

tsps I2C stop condition setup 0.6 μs

tvd Valid-data time SCL low to SDA output valid 1.2 μs

CbI2C bus capacitive load 400 pF

(1) Cb= total bus capacitance of one bus line in pF

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l TEXAS INSTRUMENTS «no mu

Supply Current (mA)

5.04.53.5 4.03.02.5

100

fSCL = 400 kHz

All I/Os unloaded

Supply Voltage (V)

2.0 5.5

0.0 0.1 0.2 0.3 0.4 0.5 0.6

VCC = 5 V

TA= −40ºC

TA= 25ºC

TA= 85ºC

VOL (V)

ISINK (mA)

Temperature (°C)

Supply Current (mA)

1007525 500−25

100

fSCL = 400 kHz

All I/Os unloaded

VCC = 5 V

−50 125

Temperature (°C)

Supply Current (mA)

1007525 500−25

−50

SCL = VCC

All I/Os unloaded

VCC = 5 V

125

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SCPS123F –MARCH 2005–REVISED JANUARY 2015

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6.7 Switching Characteristics

over recommended operating free-air temperature range, CL≤100 pF (unless otherwise noted) (see Figure 8 and Figure 9)

FROM TO

PARAMETER MIN MAX UNIT

(INPUT) (OUTPUT)

tiv Interrupt valid time P port INT 4 μs

tir Interrupt reset delay time SCL INT 4 μs

tpv Output data valid SCL P port 4 μs

tsu Input data setup time P port SCL 0 μs

thInput data hold time P port SCL 4 μs

6.8 Typical Characteristics

TA= 25°C (unless otherwise noted)

Figure 1. Supply Current vs Temperature Figure 2. Standby Supply Current vs Temperature

Figure 4. I/O Sink Current vs Output Low Voltage

Figure 3. Supply Current vs Supply Voltage

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l TEXAS INSTRUMENTS ADO suo

Temperature (°C)

10075−25 0 25 50

100

150

200

250

300

350

400

VCC = 5 V,ISINK= 10 mA

VCC = 5 V,ISINK = 1mA

VOL (mV)

125−50

Temperature (°C)

1007550250−25

100

200

300

400

500

VCC = 5 V, ISOURCE = 10 mA

VCC − VOH (V)

−50 125

PCF8575C

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SCPS123F –MARCH 2005–REVISED JANUARY 2015

Typical Characteristics (continued)

TA= 25°C (unless otherwise noted)

Figure 6. I/O High Voltage vs Temperature

Figure 5. I/O Output Low Voltage vs Temperature

Product Folder Links: PCF8575C

‘5‘ TEXAS INSTRUMENTS to. .oo

RL= 1 kW

VCC

CL= 50 pF

tbuf

ticr

tsth tsds

tsdh

ticf

ticr

tscl tsch

tsts

tPHL

tPLH

0.3 ×VCC

Stop

Condition

tsps

Repeat

Start

Condition

Start or

Repeat

Start

Condition

SCL

SDA

Start

Condition

(S)

Address

Bit 7

(MSB)

Data

Bit 10

(LSB)

Stop

Condition

(P)

3 Bytes for Complete Device

Programming

SDA LOAD CONFIGURATION

VOLTAGE WAVEFORMS

ticf

Stop

Condition

(P)

tsp

DUT SDA

0.7 ×VCC

0.3 ×VCC

0.7 ×VCC

R/W

Bit 0

(LSB)

ACK

(A)

Data

Bit 07

(MSB)

Address

Bit 1

Address

Bit 6

BYTE DESCRIPTION

2, 3

I2C address

P-port data

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7 Parameter Measurement Information

Figure 7. I2C Interface Load Circuit and Voltage Waveforms

Product Folder Links: PCF8575C

‘5‘ TEXAS INSTRUMENTS if I

S 0 1 0 0 A1

A2A01Data 1 1 PData 3

Start

Condition 16 Bits

(2 Data Bytes)

From Port Data From PortSlave Address (PCF8575)

R/W

87654321

tir

tsps

tiv

Address Data 1 Data 3

INT

Data

Into

Port

PnINT

R/W A

tir

0.7 ×VCC

0.3 ×VCC

0.7 ×VCC

0.3 ×VCC

0.7 ×VCC

0.3 ×VCC

0.7 ×VCC

0.3 ×VCC

INT SCL

View B−BView A−A

tiv

RL= 4.7 kΩ

VCC

CL= 100 pF

INTERRUPT LOAD CONFIGURATION

DUT INT

ACK

From Slave ACK

From Slave

Data 2

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SCPS123F –MARCH 2005–REVISED JANUARY 2015

Parameter Measurement Information (continued)

Figure 8. Interrupt Load Circuit and Voltage Waveforms

Product Folder Links: PCF8575C

:X ~—+

P00 A

0.7 ×VCC

0.3 ×VCC

SCL P17

tpv

Slave

ACK

Unstable

Data

Last Stable Bit

SDA

Write-Mode Timing (R/W = 0)

P00 A

0.7 ×VCC

0.3 ×VCC

SCL P17

0.7 ×VCC

0.3 ×VCC

tsu th

Read-Mode Timing (R/W = 1)

DUT

GND

CL= 100 pF

RL= 4.7 kΩ

VCC

SDA LOAD CONFIGURATION INTERRUPT LOAD CONFIGURATION

INT

GND

CL= 50 pF

RL= 1 kΩ

VCC

DUT SDA DUT

GND

CL= 100 pF

P-PORT LOAD CONFIGURATION

PCF8575C

SCPS123F –MARCH 2005–REVISED JANUARY 2015

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Parameter Measurement Information (continued)

Figure 9. P-Port Load Circuits and Voltage Waveforms

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SCPS123F –MARCH 2005–REVISED JANUARY 2015

8 Detailed Description

8.1 Overview

The PCF8575C provides an open-drain interrupt (INT) output, which can be connected to the interrupt input of a

microcontroller. An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After

time (tiv), the signal INT is valid. Resetting and reactivating the interrupt circuit is achieved when data on the port

is changed to the original setting, or data is read from or written to the port that generated the interrupt. Resetting

occurs in the read mode at the acknowledge (ACK) bit after the rising edge of the SCL signal or in the write

mode at the ACK bit after the falling edge of the SCL signal. Interrupts that occur during the ACK clock pulse can

be lost (or be very short), due to the resetting of the interrupt during this pulse. Each change of the I/Os after

resetting is detected and is transmitted as INT. Reading from or writing to another device does not affect the

interrupt circuit.

By sending an interrupt signal on this line, the remote I/O can inform the microcontroller if there is incoming data

on its ports, without having to communicate via the I2C bus. Thus, the PCF8575C can remain a simple slave

device.

Every data transmission to or from the PCF8575C must consist of an even number of bytes. The first data byte

in every pair refers to port 0 (P07–P00), and the second data byte in every pair refers to port 1 (P17–P10). To

write to the ports (output mode), the master first addresses the slave device, setting the last bit of the byte

containing the slave address to logic 0. The PCF8575C acknowledges and the master sends the first data byte

for P07–P00. After the first data byte is acknowledged by the PCF8575C, the second data byte (P17–P10) is

sent by the master. Once again, the PCF8575C acknowledges the receipt of the data, after which this 16-bit data

is presented on the port lines.

The number of data bytes that can be sent successively is not limited. After every two bytes, the previous data is

overwritten. When the PCF8575C receives the pairs of data bytes, the first byte is referred to as P07–P00 and

the second byte as P17–P10. The third byte is referred to as P07–P00, the fourth byte as P17–P10, and so on.

Before reading from the PCF8575C, all ports desired as input should be set to logic 1. To read from the ports

(input mode), the master first addresses the slave device, setting the last bit of the byte containing the slave

address to logic 1. The data bytes that follow on the SDA are the values on the ports. If the data on the input port

changes faster than the master can read, this data may be lost.

When power is applied to VCC, an internal power-on reset holds the PCF8575C in a reset state until VCC has

reached VPOR. At that time, the reset condition is released, and the device I2C-bus state machine initializes the

bus to its default state.

The hardware pins (A0, A1, and A2) are used to program and vary the fixed I2C address, and allow up to eight

devices to share the same I2C bus or SMBus. The fixed I2C address of the PCF8575C is the same as the

PCF8575, PCF8574, PCA9535, and PCA9555, allowing up to eight of these devices, in any combination, to

share the same I2C bus or SMBus.

Product Folder Links: PCF8575C

’V—+ 1 1H :3 0., 7%] Dﬁa W; i A F ))

To Interrupt

Logic

P07−P00

VCC

GND

D Q

Write Pulse

Data From

Shift Register

Power-On

Reset

Read Pulse

Data To

Shift Register

P17−P10

IOL

IOHT

I/O

Port

P17−P10

Shift

LP Filter

Interrupt

Logic

Input

Filter

Power-On

Reset

Read Pulse

Write Pulse

PCF8575C

GND

VCC

SDA

SCL

INT

I2C Bus

Control

P07−P00

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8.2 Functional Block Diagram

8.2.1 Simplified Block Diagram of Device

8.2.2 Simplified Schematic Diagram of Each P-Port Input/Output

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SDA

SCL

Start Condition

Stop Condition

PCF8575C

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8.3 Feature Description

8.3.1 I2C Interface

The bidirectional I2C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be

connected to a positive supply via a pullup resistor when connected to the output stages of a device. Data

transfer may be initiated only when the bus is not busy.

I2C communication with this device is initiated by a master sending a start condition, a high-to-low transition on

the SDA input/output while the SCL input is high (see Figure 10). After the start condition, the device address

byte is sent, MSB first, including the data direction bit (R/W). This device does not respond to the general call

address. After receiving the valid address byte, this device responds with an ACK, a low on the SDA input/output

during the high of the ACK-related clock pulse. The address inputs (A2–A0) of the slave device must not be

changed between the start and the stop conditions.

The data byte follows the address ACK. If the R/W bit is high, the data from this device are the values read from

the P port. If the R/W bit is low, the data are from the master, to be output to the P port. The data byte is followed

by an ACK sent from this device. If other data bytes are sent from the master, following the ACK, they are

ignored by this device. Data are output only if complete bytes are received and acknowledged. The output data is

valid at time (tpv) after the low-to-high transition of SCL, during the clock cycle for the ACK.

On the I2C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain

stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control

commands (start or stop) (see Figure 11).

A stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the

master (see Figure 10).

The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not

limited. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before the

receiver can send an ACK bit.

A slave receiver that is addressed must generate an ACK after the reception of each byte. Also, a master must

generate an ACK after the reception of each byte that has been clocked out of the slave transmitter. The device

that acknowledges has to pull down the SDA line during the ACK clock pulse so that the SDA line is stable low

during the high pulse of the ACK-related clock period (see Figure 12). Setup and hold times must be taken into

account.

A master receiver must signal an end of data to the transmitter by not generating an acknowledge (NACK) after

the last byte that has been clocked out of the slave. This is done by the master receiver by holding the SDA line

high. In this event, the transmitter must release the data line to enable the master to generate a stop condition.

Figure 10. Definition of Start and Stop Conditions

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‘5‘ TEXAS INSTRUMENTS XIX

Data Output

by Transmitter

SCL from

Master

Start

Condition

1 2 89

Data Output

by Receiver

Clock Pulse for

Acknowledgment

NACK

ACK

SDA

SCL

Data Line

Stable;

Data Valid

Change

of Data

Allowed

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Feature Description (continued)

Figure 11. Bit Transfer

Figure 12. Acknowledgment on I2C Bus

8.3.2 Interface Definition

BIT

BYTE 7 (MSB) 6 5 4 3 2 1 0 (LSB)

I2C slave address L H L L A2 A1 A0 R/W

P0x I/O data bus P07 P06 P05 P04 P03 P02 P01 P00

P1x I/O data bus P17 P16 P15 P14 P13 P12 P11 P10

Product Folder Links: PCF8575C

i TEXAS INSTRUMENTS Imegral Multiples 0' Two Sykes J u ﬂL/L FL/MqL/NNFL/l WJM dL,AfﬁrmRAM

A AS 0 1 0 0 A1A2 A0 0

Start

Condition

ACK

From Slave ACK

From Slave

Data DataSlave Address

R/W

P7 P6 1 P0 P7 P0 A

Integral Multiples of Two Bytes

tpv

IOHT

tir

SCL

SDA

Write to

Port

Data Output

Voltage

P5 Output

Voltage

P5 Pullup

Output

Current

INT

ACK

From Slave

Data A0

and B0

Valid

12 3 4 5678 1234567 8 1 2 3 4 5 6 7 8

IOH

PCF8575C

www.ti.com

SCPS123F –MARCH 2005–REVISED JANUARY 2015

8.3.3 Address Reference

INPUTS I2C BUS SLAVE I2C BUS SLAVE

8-BIT READ 8-BIT WRITE

A2 A1 A0 ADDRESS ADDRESS

L L L 65 (decimal), 41 64 (decimal), 40

(hexadecimal) (hexadecimal)

L L H 67 (decimal), 43 66 (decimal), 42

(hexadecimal) (hexadecimal)

L H L 69 (decimal), 45 68 (decimal), 44

(hexadecimal) (hexadecimal)

L H H 71 (decimal), 47 70 (decimal), 46

(hexadecimal) (hexadecimal)

H L L 73 (decimal), 49 72 (decimal), 48

(hexadecimal) (hexadecimal)

H L H 75 (decimal), 4B 74 (decimal), 4A

(hexadecimal) (hexadecimal)

H H L 77 (decimal), 4D 76 (decimal), 4C

(hexadecimal) (hexadecimal)

H H H 79 (decimal), 4F 78 (decimal), 4E

(hexadecimal) (hexadecimal)

8.4 Device Functional Modes

Figure 13 and Figure 14 show the address and timing diagrams for the write and read modes, respectively.

Figure 13. Write Mode (Output)

Product Folder Links: PCF8575C

l TEXAS INSTRUMENTS ﬂfLWﬂJUVUXK/XJLWW‘Mquﬂﬂfﬂﬂ/‘quW‘J \ 1n 1h :X \ a + X X 7T H_| 1 ﬂXf 4% 4#

A AS 0 1 0 0 A1A2 A0 1

ACK

From Slave

ACK

From Master

R/W

P7 P6 P0 P7

ACK

From Master

tsu

tir

SCL

SDA

Read From

Port

Data Into

Port

INT

P5 P4 P3 P2 P1 AP0

tir

tiv

P7 to P0

P6 P5 P4 P3 P2 P1

P7 P6

123456 7 8 1 2 3 4 5 67 8 1 2 3 4 5 6 7 8

P7 to P0

PCF8575C

SCPS123F –MARCH 2005–REVISED JANUARY 2015

www.ti.com

Device Functional Modes (continued)

Figure 14. Read Mode (Input)

Product Folder Links: PCF8575C

SDA

SCL

INT

GND

P06

P00

P01

P02

P03

P04

P05

P07

INT

GND

VCC

VCC 10 k (1)

Ω10 k (1)

Ω10 kΩ2 kΩ100 kΩ

(x3)

Master

Controller

PCF8575C

INT

RESET

Subsystem 2

(e.g., counter)

Subsystem 3

(e.g., alarm system)

ALARM

Controlled Device

(e.g., CBT device)

ENABLE

VCC

Subsystem 1

(e.g., temperature sensor)

SDA

SCL

P10 13

P11 14

P12 15

P13 16

P14 17

P15 18

P16 19

P17 20

PCF8575C

www.ti.com

SCPS123F –MARCH 2005–REVISED JANUARY 2015

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

Figure 15 shows an application in which the PCF8575C can be used.

9.2 Typical Application

(1) The SCL and SDA pins must be tied directly to VCC because if SCL and SDA are tied to an auxiliary power supply

that could be powered on while VCC is powered off, then the supply current, ICC, will increase as a result.

A. Device address is configured as 0100000 for this example.

B. P0, P2, and P3 are configured as outputs.

C. P1, P4, and P5 are configured as inputs.

D. P6 and P7 are not used and must be configured as outputs.

Figure 15. Application Schematic

Product Folder Links: PCF8575C

l TEXAS INSTRUMENTS 5v

LED

3.3 V 5 V

LEDx

VCC

LED

LEDx

VCC

100 kΩ

VCC

PCF8575C

SCPS123F –MARCH 2005–REVISED JANUARY 2015

www.ti.com

Typical Application (continued)

9.2.1 Design Requirements

9.2.1.1 Minimizing ICC When I/Os Control LEDs

When the I/Os are used to control LEDs, normally they are connected to VCC through a resistor as shown in

Figure 15. For a P-port configured as an input, ICC increases as VIbecomes lower than VCC. The LED is a diode,

with threshold voltage VT, and when a P-port is configured as an input the LED will be off but VIis a VTdrop

below VCC.

For battery-powered applications, it is essential that the voltage of P-ports controlling LEDs is greater than or

equal to VCC when the P-ports are configured as input to minimize current consumption. Figure 16 shows a high-

value resistor in parallel with the LED. Figure 17 shows VCC less than the LED supply voltage by at least VT.

Both of these methods maintain the I/O VIat or above VCC and prevents additional supply current consumption

when the P-port is configured as an input and the LED is off.

Figure 16. High-Value Resistor in Parallel With LED

Figure 17. Device Supplied by a Lower Voltage

Product Folder Links: PCF8575C

l TEXAS INSTRUMENTS

Cb (pF)

Rp(max) (kOhm)

0 50 100 150 200 250 300 350 400 450

D008

Standard-mode

Fast-mode

VCC (V)

Rp(min) (kOhm)

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5

0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.8

D009

VCC > 2V

VCC <= 2

p(max)

R0.8473 C

CC OL(max)

p(min)

V V

PCF8575C

www.ti.com

SCPS123F –MARCH 2005–REVISED JANUARY 2015

Typical Application (continued)

9.2.2 Detailed Design Procedure

The pull-up resistors, RP, for the SCL and SDA lines need to be selected appropriately and take into

consideration the total capacitance of all slaves on the I2C bus. The minimum pull-up resistance is a function of

VCC, VOL,(max), and IOL:

(1)

The maximum pull-up resistance is a function of the maximum rise time, tr(300 ns for fast-mode operation, fSCL =

400 kHz) and bus capacitance, Cb:

(2)

The maximum bus capacitance for an I2C bus must not exceed 400 pF for standard-mode or fast-mode

operation. The bus capacitance can be approximated by adding the capacitance of the TCA9534, Cifor SCL or

Cio for SDA, the capacitance of wires/connections/traces, and the capacitance of additional slaves on the bus.

9.2.3 Application Curves

Standard-mode Fast-mode VOL = 0.2*VCC, IOL = 2 mA

when VCC ≤2 V

(fSCL= 100 kHz, tr= 1 µs) (fSCL= 400 kHz, tr= 300 ns) VOL = 0.4 V, IOL = 3 mA

Figure 18. Maximum Pull-Up resistance (Rp(max)) vs Bus when VCC > 2 V

Capacitance (Cb)Figure 19. Minimum Pull-Up Resistance (Rp(min)) vs Pull-Up

Reference Voltage (VCC)

Product Folder Links: PCF8575C

‘5‘ TEXAS INSTRUMENTS

VCC

Ramp-Up

Time to Re-Ramp

Time

Ramp-Down

VIN drops below POR levels

VCC_RT

VCC_FT

VCC_TRR_VPOR50

VCC

Ramp-Up Re-Ramp-Up

Time to Re-Ramp

Time

Ramp-Down

VCC_RT VCC_RT

VCC_FT

VCC_TRR_GND

PCF8575C

SCPS123F –MARCH 2005–REVISED JANUARY 2015

www.ti.com

10 Power Supply Recommendations

10.1 Power-On Reset Requirements

In the event of a glitch or data corruption, PCF8575C can be reset to its default conditions by using the power-on

reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This

reset also happens when the device is powered on for the first time in an application.

The two types of power-on reset are shown in Figure 20 and Figure 21.

Figure 20. VCC is Lowered Below 0.2 V or 0 V and Then Ramped Up to VCC

Figure 21. VCC is Lowered Below the POR Threshold, Then Ramped Back Up to VCC

Table 1 specifies the performance of the power-on reset feature for PCF8575C for both types of power-on reset.

Table 1. RECOMMENDED SUPPLY SEQUENCING AND RAMP RATES(1)

PARAMETER MIN TYP MAX UNIT

VCC_FT Fall rate See Figure 20 1 100 ms

VCC_RT Rise rate See Figure 20 0.01 100 ms

VCC_TRR_GND Time to re-ramp (when VCC drops to GND) See Figure 20 0.001 ms

VCC_TRR_POR50 Time to re-ramp (when VCC drops to VPOR_MIN – 50 mV) See Figure 21 0.001 ms

Level that VCCP can glitch down to, but not cause a functional

VCC_GH See Figure 22 1.2 V

disruption when VCCX_GW = 1 μs

Glitch width that will not cause a functional disruption when

VCC_GW See Figure 22 μs

VCCX_GH = 0.5 × VCCx

VPORF Voltage trip point of POR on falling VCC 0.767 1.144 V

VPORR Voltage trip point of POR on fising VCC 1.033 1.428 V

(1) TA= –40°C to 85°C (unless otherwise noted)

Product Folder Links: PCF8575C

‘5‘ TEXAS INSTRUMENTS

VCC

VPOR

VPORF

Time

POR

Time

VCC

Time

VCC_GH

VCC_GW

PCF8575C

www.ti.com

SCPS123F –MARCH 2005–REVISED JANUARY 2015

Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width

(VCC_GW) and height (VCC_GH) are dependent on each other. The bypass capacitance, source impedance, and

device impedance are factors that affect power-on reset performance. Figure 22 and Table 1 provide more

information on how to measure these specifications.

Figure 22. Glitch Width and Glitch Height

VPOR is critical to the power-on reset. VPOR is the voltage level at which the reset condition is released and all the

registers and the I2C/SMBus state machine are initialized to their default states. The value of VPOR differs based

on the VCC being lowered to or from 0. Figure 23 and Table 1 provide more details on this specification.

Figure 23. VPOR

Product Folder Links: PCF8575C

l TEXAS INSTRUMENTS

PCF8575C

SCPS123F –MARCH 2005–REVISED JANUARY 2015

www.ti.com

11 Layout

11.1 Layout Guidelines

For printed circuit board (PCB) layout of the PCF8575C device, common PCB layout practices should be

followed but additional concerns related to high-speed data transfer such as matched impedances and

differential pairs are not a concern for I2C signal speeds.

In all PCB layouts, it is a best practice to avoid right angles in signal traces, to fan out signal traces away from

each other upon leaving the vicinity of an integrated circuit (IC), and to use thicker trace widths to carry higher

amounts of current that commonly pass through power and ground traces. By-pass and de-coupling capacitors

are commonly used to control the voltage on the VCC pin, using a larger capacitor to provide additional power in

the event of a short power supply glitch and a smaller capacitor to filter out high-frequency ripple. These

capacitors should be placed as close to the PCF8575C as possible. These best practices are shown in

Figure 24.

For the layout example provided in Figure 24, it would be possible to fabricate a PCB with only 2 layers by using

the top layer for signal routing and the bottom layer as a split plane for power (VCC) and ground (GND). However,

a 4 layer board is preferable for boards with higher density signal routing. On a 4 layer PCB, it is common to

route signals on the top and bottom layer, dedicate one internal layer to a ground plane, and dedicate the other

internal layer to a power plane. In a board layout using planes or split planes for power and ground, vias are

placed directly next to the surface mount component pad which needs to attach to VCC or GND and the via is

connected electrically to the internal layer or the other side of the board. Vias are also used when a signal trace

needs to be routed to the opposite side of the board, but this technique is not demonstrated in Figure 24.

Product Folder Links: PCF8575C

l TEXAS INSTRUMENTS LEGEND

VCC

To I2C Master

To I/Os

GND

To I/Os

PCF8575C

2 A1

4 P00

5 P01

6P 02

7 P03

8 17P14

18P15

19P16

20P17

22SCL

23SDA

24VCC

INT

P04

P05

P06

P07

GND P10

P11

P12

P13

To I/Os

By-pass/De-coupling

capacitors

To I2C Master

VIA to Power Plane

Power or GND Plane

VIA to GND Plane

LEGEND

PCF8575C

www.ti.com

SCPS123F –MARCH 2005–REVISED JANUARY 2015

11.2 Layout Example

Figure 24. Layout Example for PCF8575C

Product Folder Links: PCF8575C

l TEXAS INSTRUMENTS

PCF8575C

SCPS123F –MARCH 2005–REVISED JANUARY 2015

www.ti.com

12 Device and Documentation Support

12.1 Trademarks

All trademarks are the property of their respective owners.

12.2 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

12.3 Glossary

SLYZ022 —TI Glossary.

This glossary lists and explains terms, acronyms and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser based versions of this data sheet, refer to the left hand navigation.

Product Folder Links: PCF8575C

I TEXAS INSTRUMENTS

PACKAGE OPTION ADDENDUM

www.ti.com 13-Jul-2022

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

PCF8575CDB ACTIVE SSOP DB 24 60 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 PF575C Samples

PCF8575CDBE4 ACTIVE SSOP DB 24 60 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 PF575C Samples

PCF8575CDBQR ACTIVE SSOP DBQ 24 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 PCF8575C Samples

PCF8575CDBR ACTIVE SSOP DB 24 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 PF575C Samples

PCF8575CDGVR ACTIVE TVSOP DGV 24 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 PF575C Samples

PCF8575CDW ACTIVE SOIC DW 24 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 PCF8575C Samples

PCF8575CDWE4 ACTIVE SOIC DW 24 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 PCF8575C Samples

PCF8575CDWG4 ACTIVE SOIC DW 24 25 TBD Call TI Call TI -40 to 85 Samples

PCF8575CDWR ACTIVE SOIC DW 24 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 PCF8575C Samples

PCF8575CPW ACTIVE TSSOP PW 24 60 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 PF575C Samples

PCF8575CPWR ACTIVE TSSOP PW 24 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 PF575C Samples

PCF8575CRGER ACTIVE VQFN RGE 24 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 PF575C Samples

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

Addendum-Page 1

TEXAS INSTRUMENTS

PACKAGE OPTION ADDENDUM

www.ti.com 13-Jul-2022

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

I TEXAS INSTRUMENTS 5:. V.’

PACKAGE MATERIALS INFORMATION

www.ti.com 9-Aug-2022

TAPE AND REEL INFORMATION

Reel Width (W1)

REEL DIMENSIONS

Dimension designed to accommodate the component length

Dimension designed to accommodate the component thickness

Overall width of the carrier tape

Pitch between successive cavity centers

Dimension designed to accommodate the component width

TAPE DIMENSIONS

K0 P1

B0 W

Cavity

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Pocket Quadrants

Sprocket Holes

Q1 Q1Q2 Q2

Q3 Q3Q4 Q4 User Direction of Feed

Reel

Diameter

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

PCF8575CDBQR SSOP DBQ 24 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1

PCF8575CDBR SSOP DB 24 2000 330.0 16.4 8.2 8.8 2.5 12.0 16.0 Q1

PCF8575CDGVR TVSOP DGV 24 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

PCF8575CDWR SOIC DW 24 2000 330.0 24.4 10.75 15.7 2.7 12.0 24.0 Q1

PCF8575CPWR TSSOP PW 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1

PCF8575CRGER VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com 9-Aug-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

PCF8575CDBQR SSOP DBQ 24 2500 356.0 356.0 35.0

PCF8575CDBR SSOP DB 24 2000 356.0 356.0 35.0

PCF8575CDGVR TVSOP DGV 24 2000 356.0 356.0 35.0

PCF8575CDWR SOIC DW 24 2000 350.0 350.0 43.0

PCF8575CPWR TSSOP PW 24 2000 356.0 356.0 35.0

PCF8575CRGER VQFN RGE 24 3000 356.0 356.0 35.0

Pack Materials-Page 2

I TEXAS INSTRUMENTS

PACKAGE MATERIALS INFORMATION

www.ti.com 9-Aug-2022

TUBE

L - Tube length

T - Tube

height

W - Tube

width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)

PCF8575CDB DB SSOP 24 60 530 10.5 4000 4.1

PCF8575CDBE4 DB SSOP 24 60 530 10.5 4000 4.1

PCF8575CDW DW SOIC 24 25 506.98 12.7 4826 6.6

PCF8575CDWE4 DW SOIC 24 25 506.98 12.7 4826 6.6

PCF8575CPW PW TSSOP 24 60 530 10.2 3600 3.5

Pack Materials-Page 3

I TEXAS INSTRUMENTS

GENERIC PACKAGE VIEW

Images above are just a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

RGE 24 VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

4204104/H

nnm :) ‘ W # gnmnmnAT Q NOTES: INSTRUMBU'S

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

PACKAGE OUTLINE

www.ti.com

4224376 / C 07/2021

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK- NO LEAD

RGE0024C

0.08 C

0.1 C A B

0.05 C

SYMM

4.1

3.9

4.1

3.9

PIN 1 INDEX AREA

1 MAX

0.05

0.00

SEATING PLANE

2X 2.5

2.1±0.1

2.5

20X 0.5

712

24X 0.30

0.18

24X 0.50

0.30

(0.2) TYP

PIN 1 ID

(OPTIONAL)

{mm ~~~~~~~~~ J

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments

literature number SLUA271 (www.ti.com/lit/slua271).

5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

EXAMPLE BOARD LAYOUT

4224376 / C 06/2021

www.ti.com

VQFN - 1 mm max height

RGE0024C

PLASTIC QUAD FLATPACK- NO LEAD

SYMM

LAND PATTERN EXAMPLE

SCALE: 20X

(0.8)

2X(0.8)

(3.8)

( 2.1)

712

24X (0.6)

24X (0.24)

20X (0.5)

(R0.05)

SOLDER MASK DETAILS

NON SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK

DEFINED

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

METAL

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

(Ø0.2) VIA

TYP

(3.8)

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations..

EXAMPLE STENCIL DESIGN

4224376 / C 06/2021

www.ti.com

VQFN - 1 mm max height

RGE0024C

PLASTIC QUAD FLATPACK- NO LEAD

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD

80% PRINTED COVERAGE BY AREA

SCALE: 20X

(3.8)

(0.57)

TYP

(0.57)

TYP

4X ( 0.94)

712

1924

24X (0.24)

24X (0.6)

20X (0.5)

(R0.05) TYP

METAL

TYP

(3.8)

MECHANICAL DATA D31; U (324) ‘LASHC S‘WALL70L1LN¥ \JACXML 4 _ > HHHHHWHHHHHH ,,<, ,,,,,="" \\="" v="" ‘hmhhhmhhhhh="" ~="" 4073301="" *4/h="" 10/2008="" ah="" hnec'="" dimensmrs="" c'e="" m="" mc'ves="" ['m‘hmeters)="" th5="" drawer="" ‘5="" sumac:="" :0="" change="" mm:="" home,="" body="" dwmcnswons="" do="" not="" mcmae="" mom="" ﬂash="" or="" cromsm="" m="" m="" exceed="" 0006="" (055)="" per="" 3m="" fuhs="" mm="" jedec="" m07137="" vunumn="" ae,="" no’es:="" cnm=""> Q; ”Dams INSI'RUMENTS www.1i.com

I ,/ x /. \_ , ‘ .\ ,, /x ,, S 1 EL ﬁg

www.ti.com

PACKAGE OUTLINE

22X 0.65

7.15

24X 0.30

0.19

TYP

6.6

6.2

1.2 MAX

0.15

0.05

0.25

GAGE PLANE

-80

NOTE 4

4.5

4.3

NOTE 3

7.9

7.7

0.75

0.50

(0.15) TYP

TSSOP - 1.2 mm max heightPW0024A

SMALL OUTLINE PACKAGE

4220208/A 02/2017

12 13

0.1 C A B

PIN 1 INDEX AREA

SEE DETAIL A

0.1 C

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.

5. Reference JEDEC registration MO-153.

SEATING

PLANE

A 20

DETAIL A

TYPICAL

SCALE 2.000

gmmmﬂgmmﬁj ‘w“““‘+“‘w““‘ Emma—5% R

www.ti.com

EXAMPLE BOARD LAYOUT

0.05 MAX

ALL AROUND 0.05 MIN

ALL AROUND

24X (1.5)

24X (0.45)

22X (0.65)

(5.8)

(R0.05) TYP

TSSOP - 1.2 mm max heightPW0024A

SMALL OUTLINE PACKAGE

4220208/A 02/2017

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 10X

SYMM

12 13

15.000

METAL

SOLDER MASK

OPENING METAL UNDER

SOLDER MASK SOLDER MASK

OPENING

EXPOSED METAL

SOLDER MASK DETAILS

NON-SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK

DEFINED

ﬁﬂmmmmmﬁmmmﬁ$% Emma—5%g

www.ti.com

EXAMPLE STENCIL DESIGN

24X (1.5)

24X (0.45)

22X (0.65)

(5.8)

(R0.05) TYP

TSSOP - 1.2 mm max heightPW0024A

SMALL OUTLINE PACKAGE

4220208/A 02/2017

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE: 10X

SYMM

12 13

MECHANICAL DATA DW «#:5075220 JLASW‘ SMALL 0U J\L HHHHHHHHHHHH’ﬁ N A AH Hnec' d'vnensm m ‘mmes (mammaers) D'ws'nmng md tu‘ermc'mq per ASME w 5M 1994, B TH: drawmq ‘5 Sn :0 change wan: nohce. a Body dimensmns ca nut inc‘ude mom ﬂcsh ur mum" rut m exceed 0035 (055) D FONS WMHH JEDEC MSiOH vermin" ADV NOTES: {if TEXAS INSTRUMENTS wwvmi .com

oo A‘ioyi 55 ﬁHHHHHHHHHHHHﬁ {'3 TEXAS INSTRUMENTS

MECHANICAL DATA

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE

4040065 /E 12/01

28 PINS SHOWN

Gage Plane

8,20

7,40

0,55

0,95

0,25

12,90

12,30

10,50

8,50

Seating Plane

9,907,90

10,50

9,90

0,38

5,60

5,00

0,22

2016

6,50

0,05 MIN

5,905,90

DIM

A MAX

A MIN

PINS **

2,00 MAX

6,90

7,50

0,65 M

0,15

0°–ā8°

0,10

0,09

0,25

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-150

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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

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These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

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standards, and any other safety, security, regulatory or other requirements.

These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license

is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you

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TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with

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TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

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PCF8575C Datasheet by Texas Instruments

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