Details, datasheet, quote on part number: MDU3C
| Part | MDU3C |
| Category | Timing Circuits => Delay Lines |
| Description | Triple, Hcmos-interfaced Fixed Delay Line Series |
| Company | Data Delay Devices, Inc. |
| Datasheet | Download MDU3C Datasheet |
| Features, Applications |
TRIPLE, HCMOS-INTERFACED FIXED DELAY LINE (SERIES MDU3C) FEATURES Three independent delay lines Fits standard 14-pin DIP socket Low profile Auto-insertable Input & outputs fully CMOS interfaced & buffered T L fan-out capability The MDU3C-series device a 3-in-1 digitally buffered delay line. The signal inputs (I1-I3) are reproduced at the outputs (O1-O3), shifted in time by an amount determined by the device dash number (See Table). The delay lines function completely independently of each other. I1-I3 O1-O3 VDD GND Signal Inputs Signal Outputs +5 Volts GroundMinimum input pulse width: 100% of total delay Output rise time: 8ns typical Supply voltage: � 5% Supply current: ICCL = 40�a typical ICCH = 60ma typical Operating temperature: 70� C Temp. coefficient of total delay: 300 PPM/�C NOTE: Any dash number between 10 and 100 not shown is also available.The MDU3C tolerances are guaranteed for input pulse widths and periods greater than those specified in the test conditions. Although the device will function properly for pulse widths as small 100% of the total delay and periods as small 200% of the total delay (for a symmetric input), the delays may deviate from their values at low frequency. However, for a given input condition, the deviation will be repeatable from pulse to pulse. Contact technical support at Data Delay Devices if your application requires device testing at a specific input condition. The MDU3C relies on a stable power supply to produce repeatable delays within the stated tolerances. A 0.1uf capacitor from VDD to GND, located as close as possible to the VDD pin, is recommended. A wide VDD trace and a clean ground plane should be used. PARAMETER DC Supply Voltage Input Pin Voltage Storage Temperature Lead Temperature SYMBOL VDD VIN TSTRG TLEAD MIN -0.3 -55 MAX 150 300 UNITS NOTES to 5.25V) PARAMETER High Level Output Voltage Low Level Output Voltage High Level Output Current Low Level Output Current High Level Input Voltage Low Level Input Voltage Input Current SYMBOL VOH VOL IOH IOL VIH VIL IIH MIN 3.98 TYP 4.4 0.15 MAX UNITS V �A NOTES VDD = 5.0, IOH = MAX VIH = MIN, VIL = MAX VDD = 5.0, IOL = MAX VIH = MIN, VIL = MAX |
| Related products with the same datasheet |
| MDU3C-10 |
| MDU3C-100 |
| MDU3C-100A2 |
| MDU3C-100B2 |
| MDU3C-100M |
| MDU3C-100MC2 |
| MDU3C-15 |
| MDU3C-20 |
| MDU3C-25 |
| MDU3C-30 |
| MDU3C-40 |
| MDU3C-50 |
| Some Part number from the same manufacture Data Delay Devices, Inc. |
| MDU3C-10 Triple, Hcmos-interfaced Fixed Delay Line Series |
| PDU1016H 4-bit, Ecl-interfaced Programmable Delay Line Series |
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DDU66F-175MD1 : 5-tap, Ttl-interfaced Fixed Delay Line DDU8F-5250MD1 : 5-tap, Ttl-interfaced Fixed Delay Line DLO32F-14 : Ttl-interfaced, Gated Delay Line Oscillator Series PDU1016H-8C4 : 4-bit, Ecl-interfaced Programmable Delay Line Series PWC11-5 : Fixed Ecl Pulse Width Controller MDU12H-40C3 : Dual, Ecl-interfaced Fixed Delay LINE (series Mdu12h) PPG38F-10C5 : 8-bit Programmable Pulse Generator (series Ppg38f) 3D3323M-30 : Monolithic Triple Fixed Delay LINE 3D7005-250 : All Silicon Delay Line 3D7428-0.5 : Monolithic 8-bit Programmable Delay LINE 1520B-20-3.0B : 10-tap Dip/smd Delay LINE Td/tr = 5 |
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