Details, datasheet, quote on part number: MB86833EVKT
| Part | MB86833EVKT |
| Category | Unsorted |
| Description | Mb86833 Evaluation Kit |
| Company | Fujitsu Microelectronics, Inc. |
| Datasheet | Download MB86833EVKT Datasheet |
| Features, Applications |
DESCRIPTION Fujitsu introduces a full-featured, low-cost evaluation kit for the SPARCliteTM RISC processor. The kit includes a board module and software to allow users to evaluate SPARClite's performance. The GNU-C cross compiler included in the kit is DOS hosted. It is optimized for SPARClite and can produce executable code for the entire SPARClite family of products. It will also be possible for users to debug the test code with the GNU GDB software. This tool is resident in the PC Windows environment and provides a user friendly Windows interface. This tool offers feature rich debugging commands such as single stepping and software and hardware breakpointing. It also displays the registers, flags, assembly, and C with assembly interlaced. Rather than using software simulation, code can actually be debugged on the evaluation board itself. A variety of tools and libraries are available to the users. In addition to serving as an evaluation tool, this kit will also be a stepping stone to software development and hardware expansion. - Minimum 8MB RAM - Minimum 30MB Hard Disk Space - Minimum Windows� 3.1 - CD-ROM Drive n PC/AT Power Supply n Cables n Secondary ASCII Terminal - MB86833 SPARClite 66 MHz Processor - 4MByte DRAM Memory - 2 Serial Ports n SPARClite Evaluation Kit CD - GNU C Development Tools - MB86833 Data Sheet and User Manual - SPARClite Evaluation Board Software - SPARClite Evaluation Kit Manuals - UNIX� (SUNOS 4.X and Solaris 2.X) version of the GNU C Development Tools and the SPARClite Software n 66 MHz version with clock doubling n SPARC� high performance RISC architecture Bus interface support for or 32-bit memories n Support for burst mode cache fills n Built-in DRAM & EDO DRAM controller n Interrupt Controller with fast interrupt response time, 8 window, 136 word register file 16 address spaces, 256 MByte each Harvard-style separate instruction and data buses on-chip 1 Kbytes 2-way set associative instruction cache 1 Kbytes 2-way set associative data cache Flexible locking mechanism for data and instruction cache entries Option to force non-cached operation based on chip selects on Non-Cache Pin Four deep buffered writes and one deep instruction pre-fetching Core can run to 5 times the frequency of the Bus Interface Unit (Maximum BIU Speed Limited to 40 MHz) with programmable priority Sleep mode support Programmable address decoder and wait-state generator On-chip clock generator circuit Single vector trapping Power down modes, with global or selective power down 0.35 micron gate, 2 level metal CMOS technology, 3.3V internal and 3.3/5.0V I/O SPARClite is a trademark of SPARC International, Inc., licensed exclusively to Fujitsu Microelectronics Inc. All trademarks or registered trademarks are the property of their respective owners. SPARC is a registered trademark of SPARC International, Inc., based on technology developed by Sun Microsystems, Inc. Printed in the U.S.A. 3545 North First Street, San Jose, California 95134-1804 Customer Response Center (CRC) CRC Tel: 1-800-866-8608, CRC Fax: 408-922-9179 http://www.fujitsumicro.com |
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