LPC2880, 2888 Datasheet by NXP USA Inc.

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1. General description

The LPC2880/2888 is an ARM7-based microcontroller for portable applications requiring

low power and high performance. It includes a USB 2.0 Hi-Speed device interface, an

external memory interface that can interface to SDRAM and flash, an SD/MMC memory

card interface, ADC and DACs, and serial interfaces including UART, I2C-bus, and

I2S-bus. Architectural enhancements like multi-channel DMA, processor cache,

simultaneous operations on multiple internal buses, and flexible clock generation help

ensure that the LPC2880/2888 can handle more demanding applications than many

competing devices. The chip can be powered from a single battery, from the USB, or from

regulated 1.8 V and 3.3 V.

2. Features

2.1 Key features

nARM7TDMI processor with 8 kB cache, operating at up to 60 MHz

n1 MB on-chip flash program memory with 128-bit access for high performance

n64 kB SRAM

nBoot ROM allows execution of flash code, external code, or flash programming via

USB

nOn-chip DC-to-DC converter can generate all required voltages from a single battery

or from USB power

nMultiple internal buses allow simultaneous simple DMA, USB DMA, and program

execution from on-chip flash without contention

nExternal memory controller supports flash, SRAM, ROM, and SDRAM

nAdvanced vectored interrupt controller, supporting up to 30 vectored interrupts

nInnovative event router allows interrupt, power-up, and clock-start capabilities from up

to 107 sources

nMulti-channel general purpose DMA controller that can be used with most on-chip

peripherals as well as for memory-to-memory transfers

nSerial interfaces:

uHi-Speed or Full-Speed USB 2.0 device (480 Mbit/s or 12 Mbit/s) with on-chip

physical layer

uUART with fractional baud rate generation, flow control, IrDA support, and FIFOs

uI2C-bus interface

uI2S-bus (Inter IC Sound bus) interface for independent stereo digital audio input

and output

nSD/MMC memory card interface

LPC2880; LPC2888

16/32-bit ARM microcontrollers; 8 kB cache, up to 1 MB flash,

Hi-Speed USB 2.0 device, and SDRAM memory interface

Rev. 03 — 17 April 2008 Preliminary data sheet

Preliminary data sheet Rev. 03 — 17 April 2008 2 of 43

NXP Semiconductors LPC2880; LPC2888

16/32-bit ARM microcontrollers with external memory interface

n10-bit ADC with 5-channel input multiplexing

n16-bit stereo ADC and DACs with gain control

nAdvanced clock generation and power control reduce power consumption

nTwo 32-bit timers with selectable prescalers

n8-bit/4-bit LCD interface bus

nReal-Time Clock (RTC) can be clocked by 32 kHz oscillator or another source

nWatchdog timer with interrupt and/or reset capabilities

3. Ordering information

3.1 Ordering options

[1] JTAG interface disabled to provide code read protection. These devices are meant for volume production (no JTAG debugging is

possible). The on-chip flash on these devices can only be programmed via USB.

Table 1. Ordering information

Type number Package

Name Description Version

LPC2880FET180 TFBGA180 plastic thin fine-pitch ball grid array package;

180 balls; body 10 × 10 × 0.8 mm SOT640-1

LPC2888FET180/01 TFBGA180 plastic thin fine-pitch ball grid array package;

180 balls; body 10 × 10 × 0.8 mm SOT640-1

LPC2888FET180/D1 TFBGA180 plastic thin fine-pitch ball grid array package;

180 balls; body 10 × 10 × 0.8 mm SOT640-1

Table 2. Ordering options

Type number Flash memory JTAG interface RAM Temperature range

LPC2880FET180 - enabled 64 kB −40 °C to +85 °C

LPC2888FET180/01 1 MB enabled 64 kB −40 °C to +85 °C

LPC2888FET180/D1 1 MB disabled[1] 64 kB −40 °C to +85 °C

AQQQ Dam Hv Hv QQQQQQQ

Preliminary data sheet Rev. 03 — 17 April 2008 3 of 43

NXP Semiconductors LPC2880; LPC2888

16/32-bit ARM microcontrollers with external memory interface

4. Block diagram

(1) LPC2888 only.

Fig 1. Block diagram

MULTI-LAYER AHB

AIN[4:0]

Px.y

WATCHDOG

TIMER

SD/MMC CARD

INTERFACE

GENERAL

PURPOSE I/O

SYSTEM

CONTROL

EVENT

ROUTER

interface

DC-TO-DC

CONVERTER

START,

STOP

SCL, SDA

MCLK, MCMD

MD[3:0]

DATI

BCKI, WSI

AOUTA,

AOUTA_DAC,

AOUTB,

AOUTB_DAC

VREF,

AIN_LNA,

AINA, AINB

DATO

BCKO, DCLKO,

WSO

+1.5 V

or +5 V

3.3 V,

1.8 V

XTALI

XTALO

X32I

X32O

CLOCK

GENERATION

UNIT

OSCILLATOR

AND PLLs

ARM7TDMI

JTAG DEBUG

INTERFACE

8 kB CACHE

JTAG_TRST

JTAG_TMS

JTAG_TCK

JTAG_TDI

JTAG_TDO

JTAG_SEL

FLASH

INTERFACE

1 MB

FLASH(1)

SRAM

INTERFACE

64 kB

SRAM

ROM

INTERFACE

BOOT

ROM

REAL-TIME

CLOCK

OSCILLATOR

FIFO FIFO I2S-BUS

INPUT

FIFO I2S-BUS

OUTPUT

TRIPLE ANALOG

INPUT

FIFO

DUAL ANALOG

OUTPUT

EXTERNAL

MEMORY

CONTROLLER

A[20:0],

D[15:0],

etc.

VECTORED

INTERRUPT

CONTROLLER

HS USB

WITH DMA

DP, DM, VBUS,

RREF, RPU

LPC2880/2888

AHB TO APB

BRIDGE 0

AHB TO APB

BRIDGE 3

AHB TO APB

BRIDGE 1 AHB TO APB

BRIDGE 2 GP DMA

CONTROLLER

10-BIT A/D

CONVERTER

AOUT_LNA

UART WITH

IrDA

TXD, RTS

RXD, CTS

LCD

INTERFACE LCD bus

I2C-BUS

INTERFACE

32-BIT

TIMER 0

32-BIT

TIMER 1

002aac296

000 000 000 000 000 000 000 000 000 000 000 000 000000000000000 000000000000000 000000000000000 000000000000000 000000000000000 000000000000000 oooooooooooooooooo Oooooooooooooooooo oooooooooooooooooo

Preliminary data sheet Rev. 03 — 17 April 2008 4 of 43

NXP Semiconductors LPC2880; LPC2888

16/32-bit ARM microcontrollers with external memory interface

5. Pinning information

5.1 Pinning

Fig 2. Pin configuration

Table 3. Pin allocation table

Pin Symbol Pin Symbol Pin Symbol Pin Symbol

Row A

1 D0/P0[0] 2 D1/P0[1] 3 D3/P0[3] 4 D4/P0[4]

5 D6/P0[6] 6 VSS2(EMC) 7V

DD2(EMC) 8 STCS1/P1[6]

9RAS/P1[17] 10 MCLKO/P1[14] 11 DQM1/P1[11] 12 BLS0/P1[12]

13 A18/P1[2] 14 A15/P0[31] 15 VSS1(EMC) 16 VDD1(EMC)

17 OE/P1[18] 18 A6/P0[22] - -

Row B

1RPO/P1[19] 2 D2/P0[2] 3 LCS/P4[0] 4 D5/P0[5]

5 D7/P0[7] 6 D11/P0[11] 7 D13/P0[13] 8 D15/P0[15]

9DYCS/P1[8] 10 CKE/P1[9] 11 STCS2/P1[7] 12 BLS1/P1[13]

13 A19/P1[3] 14 A16/P1[0] 15 A13/P0[29] 16 A11/P0[27]

17 A9/P0[25] 18 A7/P0[23] - -

Row C

1 LD1/P4[5] 2 LD0/P4[4] 3 LD2/P4[6] 4 D8/P0[8]

5 D9/P0[9] 6 D10/P0[10] 7 D12/P0[12] 8 D14/P0[14]

9STCS0/P1[5] 10 CAS/P1[16] 11 WE/P1[15] 12 DQM0/P1[10]

13 A20/P1[4] 14 A17/P1[1] 15 A14/P0[30] 16 A12/P0[28]

17 A10/P0[26] 18 A8/P0[24] - -

Row D

1 LD4/P4[8] 2 LD3/P4[7] 3 LD5/P4[9] 4 -

002aac239

LPC2880FET180

LPC2888FET180/01

LPC2888FET180/D1

Transparent top view

24681012

131415 17

16 18

1357911

ball A1

index area

Preliminary data sheet Rev. 03 — 17 April 2008 5 of 43

NXP Semiconductors LPC2880; LPC2888

16/32-bit ARM microcontrollers with external memory interface

13 - 14 - 15 - 16 A3/P0[19]

17 A4/P0[20] 18 A5/P0[21] - -

Row E

DD1(IO3V3) 2 LD6/P4[10] 3 LD7/P4[11] 4 -

13 - 14 - 15 - 16 A0/P0[16]

17 A1/P0[17] 18 A2/P0[18] - -

Row F

SS1(IO) 2 LER/P4[3] 3 LRS/P4[1] 4 -

13 - 14 - 15 - 16 DCLKO/P3[3]

17 DATO/P3[6] 18 WSO - -

Row G

SS1(CORE) 2 LRW/P4[2] 3 MCLK/P5[0] 4 -

13 - 14 - 15 - 16 DATI/P3[0]

17 WSI/P3[2] 18 BCKO/P3[5] - -

Row H

DD1(CORE1V8) 2 MCMD/P5[1] 3 MD0/P5[5] 4 -

13 - 14 - 15 - 16 SCL

17 BCKI/P3[1] 18 VSS4(IO) --

Row J

1 MD2/P5[3] 2 MD1/P5[4] 3 MD3/P5[2] 4 -

13 - 14 - 15 - 16 MODE2/P2[3]

17 SDA 18 VDD4(IO3V3) --

Row K

1RTS/P6[3] 2 CTS/P6[2] 3 RXD/P6[0] 4 -

13 - 14 - 15 - 16 P2[0]

17 P2[1] 18 MODE1/P2[2] - -

Row L

DD(DAC3V3) 2 VREFP(DAC) 3 TXD/P6[1] 4 -

13 - 14 - 15 - 16 DCDC_GND

17 START 18 STOP - -

Row M

1 VREFN(DAC) 2 AOUTL 3 AOUTR 4 -

13 - 14 - 15 - 16 DCDC_VDDI(3V3)

17 DCDC_VBAT 18 DCDC_CLEAN - -

Row N

1 i.c.[1] 2 i.c.[1] 3 i.c.[1] 4-

13 - 14 - 15 - 16 DCDC_VSS2

17 DCDC_LX2 18 DCDC_VDDO(1V8) --

Row P

SS6(IO) 2V

SS5(IO) 3 i.c.[1] 4-

13 - 14 - 15 - 16 RREF

Table 3. Pin allocation table

…continued

Pin Symbol Pin Symbol Pin Symbol Pin Symbol

Preliminary data sheet Rev. 03 — 17 April 2008 6 of 43

NXP Semiconductors LPC2880; LPC2888

16/32-bit ARM microcontrollers with external memory interface

[1] These pins are connected internally and must be left unconnected in an application.

5.2 Pin description

17 DCDC_LX1 18 DCDC_VSS1 --

Row R

DD5(IO3V3) 2V

DD6(IO3V3) 3 i.c.[1] 4-

13 - 14 - 15 - 16 VSS2(USB)

17 VSS1(USB) 18 DCDC_VDDO(3V3) --

Row T

1 AINR 2 i.c.[1] 3V

COM(DADC) 4 AINL

5 JTAG_TDI 6 AIN3 7 AIN1 8 X32O

SS(OSC) 10 XTALI 11 VSS3(INT) 12 VSS1(INT)

13 JTAG_TRST 14 RESET 15 CONNECT 16 VSS3(USB)

17 DM 18 DCDC_VUSB --

Row U

1 VREF(DADC) 2 VREFP(DADC) 3 VDD(DADC3V3) 4 JTAG_SEL

5 AIN4 6 AIN2 7 AIN0 8 VDD(OSC321V8)

DD(OSC1V8) 10 VSS(ADC) 11 VSS2(INT) 12 JTAG_TMS

13 JTAG_TDO 14 VBUS/P7[0] 15 VDD1(USB1V8) 16 VDD2(USB1V8)

17 DP 18 VDD3(USB3V3) --

Row V

1 VREFN(DADC) 2 VSS(DADC) 3V

DD(DADC1V8) 4 JTAG_TCK

DD2(IO3V3) 6V

SS2(IO) 7 X32I 8 VSS(OSC32)

9 XTALO 10 VDD(ADC3V3) 11 VDD2(CORE1V8) 12 VSS2(CORE)

13 VSS3(IO) 14 VDD3(IO3V3) 15 VDD1(FLASH1V8) 16 VDD2(FLASH1V8)

17 VSS3(CORE) 18 VDD4(USB3V3) --

Table 3. Pin allocation table

…continued

Pin Symbol Pin Symbol Pin Symbol Pin Symbol

Table 4. Pin description

Symbol Ball # Type[1] Description

Analog in (dual converter)

AINL T4 I analog L input channel

AINR T1 I analog R input channel

VCOM(DADC) T3 RV ADC common reference voltage and analog output reference voltage

combined on-chip

VREF(DADC) U1 RV ADC reference voltage

VREFN(DADC) V1 RV ADC negative reference voltage

VREFP(DADC) U2 RV ADC positive reference voltage

VDD(DADC1V8) V3 P 1.8 V for dual ADC

VDD(DADC3V3) U3 P 3.3 V for dual ADC

VSS(DADC) V2 P ground for dual ADC

Preliminary data sheet Rev. 03 — 17 April 2008 7 of 43

NXP Semiconductors LPC2880; LPC2888

16/32-bit ARM microcontrollers with external memory interface

Analog in (single converter)

AIN0 U7 I multiplexed analog input

AIN1 T7 I multiplexed analog input

AIN2 U6 I multiplexed analog input

AIN3 T6 I multiplexed analog input

AIN4 U5 I multiplexed analog input

VDD(ADC3V3) V10 P 3.3 V analog supply and reference voltage

VSS(ADC) U10 P ground

Analog out (dual channel)

AOUTL M2 O DAC L analog out

AOUTR M3 O DAC R analog out

VREFN(DAC) M1 RV negative reference voltage

VREFP(DAC) L2 RV positive reference voltage

VDD(DAC3V3) L1 P 3.3 V for DAC

DAI interface

BCKI/P3[1] H17 FI DAI bit clock; 5 V tolerant GPIO pin

DATI/P3[0] G16 FI DAI serial data input; 5 V tolerant GPIO pin

WSI/P3[2] G17 FI DAI word select; 5 V tolerant GPIO pin

DAO interface

BCKO/P3[5] G18 FO DAO bit clock; 5 V tolerant GPIO pin

DATO/P3[6] F17 FO DAO serial data output; 5 V tolerant GPIO pin

DCLKO/P3[3] F16 FO 256 × clock output; 5 V tolerant GPIO pin

WSO F18 O DAO word select; 5 V tolerant pin

DC-to-DC converters

START L17 I DC-to-DC converter activation

STOP L18 I DC-to-DC converter deactivation

DCDC_CLEAN M18 P reference circuit ground, not connected to substrate

DCDC_GND L16 P DC-to-DC converter main ground and substrate

DCDC_LX1 P17 P connect to external coil for DC/DC1

DCDC_LX2 N17 P connect to external coil for DC/DC2

DCDC_VBAT M17 P connect to battery +

DCDC_VDDI(3V3) M16 P DC/DC1 3.3 V input voltage

DCDC_VDDO(1V8) N18 P DC/DC2 1.8 V output voltage

DCDC_VDDO(3V3) R18 P DC/DC1 3.3 V output voltage

DCDC_VSS1 P18 P ground for DC/DC1, not connected to substrate

DCDC_VSS2 N16 P ground for DC/DC2, not connected to substrate

DCDC_VUSB T18 P connect to +5 V pin of USB connector

Table 4. Pin description

…continued

Symbol Ball # Type[1] Description

Preliminary data sheet Rev. 03 — 17 April 2008 8 of 43

NXP Semiconductors LPC2880; LPC2888

16/32-bit ARM microcontrollers with external memory interface

External memory interface

D0/P0[0] A1 FI external memory data bus, low byte (I/O); GPIO pins

D1/P0[1] A2

D2/P0[2] B2

D3/P0[3] A3

D4/P0[4] A4

D5/P0[5] B4

D6/P0[6] A5

D7/P0[7] B5

D8/P0[8] C4 FI external memory data bus, high byte (I/O); GPIO pins

D9/P0[9] C5

D10/P0[10] C6

D11/P0[11] B6

D12/P0[12] C7

D13/P0[13] B7

D14/P0[14] C8

D15/P0[15] B8

A0/P0[16] E16 FO address bus for SDRAM and static memory; GPIO pins

A1/P0[17] E17

A2/P0[18] E18

A3/P0[19] D16

A4/P0[20] D17

A5/P0[21] D18

A6/P0[22] A18

A7/P0[23] B18

A8/P0[24] C18

A9/P0[25] B17

A10/P0[26] C17

A11/P0[27] B16

A12/P0[28] C16

A13/P0[29] B15

A14/P0[30] C15

A15/P0[31] A14 FO address bus for static memory; GPIO pins

A16/P1[0] B14

A17/P1[1] C14

A18/P1[2] A13

A19/P1[3] B13

A20/P1[4] C13

BLS0/P1[12] A12 FO byte lane select for D[7:0], active LOW for static memory; GPIO pin

BLS1/P1[13] B12 FO byte lane select for D[15:8], active LOW for static memory; GPIO pin

CAS/P1[16] C10 FO column address strobe, active LOW for SDRAM; GPIO pin

Table 4. Pin description

…continued

Symbol Ball # Type[1] Description

Preliminary data sheet Rev. 03 — 17 April 2008 9 of 43

NXP Semiconductors LPC2880; LPC2888

16/32-bit ARM microcontrollers with external memory interface

CKE/P1[9] B10 FO clock enable; active HIGH for SDRAM; GPIO pin

DQM0/P1[10] C12 FO data mask output for D[7:0], active HIGH for SDRAM; GPIO pin

DQM1/P1[11] A11 FO data mask output for D[15:8], active HIGH for SDRAM; GPIO pin

DYCS/P1[8] B9 FO chip select, active LOW for SDRAM; GPIO pin

MCLKO/P1[14] A10 FO clock for SDRAM and SyncFlash memory; GPIO pin

OE/P1[18] A17 FO output enable, active LOW for static memory; GPIO pin

RAS/P1[17] A9 FO row address strobe, active LOW for SDRAM; GPIO pin

RPO/P1[19] B1 FO reset power-down, active LOW for SyncFlash memory; GPIO pin

STCS0/P1[5] C9 FO chip select, active LOW for static memory bank 0; GPIO pin

STCS1/P1[6] A8 FO chip select, active LOW for static memory bank 1; GPIO pin

STCS2/P1[7] B11 FO chip select, active LOW for static memory bank 2; GPIO pin

WE/P1[15] C11 FO write enable, active LOW for SDRAM and static memory; GPIO pin

GPIO and mode control

MODE1/P2[2] K18 FI start-up mode pin 1 (pull-down); 5 V tolerant GPIO pin

MODE2/P2[3] J16 FI start-up mode pin 2 (pull-down); 5 V tolerant GPIO pin

P2[0] K16 FI 5 V tolerant GPIO pin

P2[1] K17 FI 5 V tolerant GPIO pin

I2C-bus interface

SCL H16 I/O serial clock (input/open-drain output); 5 V tolerant pin

SDA J17 I/O serial data (input/open-drain output); 5 V tolerant pin

JTAG interface

JTAG_SEL U4 I JTAG selection (pull-down); 5 V tolerant pin

JTAG_TCK V4 I JTAG reset input (pull-down); 5 V tolerant pin

JTAG_TDI T5 I JTAG data input (pull-up); 5 V tolerant pin

JTAG_TMS U12 I JTAG mode select input (pull-up); 5 V tolerant pin

JTAG_TRST T13 I JTAG reset input (pull-down); 5 V tolerant pin

JTAG_TDO U13 O JTAG data output; 5 V tolerant pin

LCD interface

LCS/P4[0] B3 FO chip select to LCD device, programmable polarity; 5 V tolerant GPIO pin

LD0/P4[4] C2 FO data bus to/from LCD (I/O) or 5 V tolerant GPIO pins

LD1/P4[5] C1 FO

LD2/P4[6] C3 FO

LD3/P4[7] D2 FO

LD4/P4[8] D1 FO

LD5/P4[9] D3 FO

LD6/P4[10] E2 FO

LD7/P4[11] E3 FO

LER/P4[3] F2 FO 6800 E or 8080 RD or 5 V tolerant GPIO pin

LRS/P4[1] F3 FO ‘HIGH’ data register select, ‘LOW’ instruction register select, or 5 V tolerant

GPIO pin

LRW/P4[2] G2 FO 6800 W/R or 8080 WR or 5 V tolerant GPIO pin

Table 4. Pin description

…continued

Symbol Ball # Type[1] Description

Preliminary data sheet Rev. 03 — 17 April 2008 10 of 43

NXP Semiconductors LPC2880; LPC2888

16/32-bit ARM microcontrollers with external memory interface

Memory card interface

MCMD/P5[1] H2 FI command (I/O); 5 V tolerant GPIO pin

MD0/P5[5] H3 FI data bus from/to SD/MCI card (I/O); 5 V tolerant GPIO pin

MD1/P5[4] J2 FI data bus from/to SD/MCI card (I/O); 5 V tolerant GPIO pin

MD2/P5[3] J1 FI data bus from/to SD/MCI card (I/O); 5 V tolerant GPIO pin

MD3/P5[2] J3 FI data bus from/to SD/MCI card (I/O); 5 V tolerant GPIO pin

MCLK/P5[0] G3 FO MCI clock output; 5 V tolerant GPIO pin

Oscillator (32.768 kHz)

X32I V7 I 32.768 kHz oscillator input

X32O T8 O 32.768 kHz oscillator output

VDD(OSC321V8) U8 P 1.8 V

VSS(OSC32) V8 P ground

Oscillator (main)

XTALI T10 I main oscillator input

XTALO V9 O main oscillator output

VDD(OSC1V8) U9 P 1.8 V

VSS(OSC) T9 P ground

Reset

RESET T14 I master reset, active LOW; 5 V tolerant pin

UART

CTS/P6[2] K2 FI clear to send or transmit flow control, active LOW; 5 V tolerant GPIO pin

RXD/P6[0] K3 FI serial input; 5 V tolerant GPIO pin

RTS/P6[3] K1 FO request to send or receive flow control, active LOW; 5 V tolerant GPIO pin

TXD/P6[1] L3 FO serial output; 5 V tolerant GPIO pin

USB interface

CONNECT T15 P used for signalling speed capability; for high-speed USB, connect an external

1.5 kΩ resistor to 3.3 V

DM T17 I/O negative USB data line

DP U17 I/O positive USB data line

RREF P16 P transceiver reference; connect an external 12 kΩ 1 % resistor to ground

VBUS/P7[0] U14 FI USB supply detection; 5 V tolerant GPIO pin

VDD1(USB1V8) U15 P analog 1.8 V

VDD2(USB1V8) U16 P analog 1.8 V

VDD3(USB3V3) U18 P analog 3.3 V

VDD4(USB3V3) V18 P analog 3.3 V

VSS1(USB) R17 P analog ground

VSS2(USB) R16 P analog ground

VSS3(USB) T16 P analog ground

Table 4. Pin description

…continued

Symbol Ball # Type[1] Description

Preliminary data sheet Rev. 03 — 17 April 2008 11 of 43

NXP Semiconductors LPC2880; LPC2888

16/32-bit ARM microcontrollers with external memory interface

[1] I = input; O = output; I/O = input/output; RV = reference voltage; FI = functional input; FO = functional output; P = power or ground

6. Functional description

6.1 Architectural overview

The LPC2880/2888 includes an ARM7TDMI CPU with an 8 kB cache, an AMBA AHB

interfacing to high-speed on-chip peripherals and internal and external memory, and four

AMBA APBs for connection to other on-chip peripheral functions.

The LPC2880/2888 includes a multi-layer AHB and four separate APBs, in order to

minimize interference between the USB controller, other DMA operations, and processor

activity. Bus masters include the ARM7 itself, the USB block, and the general purpose

DMA controller.

Digital power and ground

VDD1(CORE1V8) H1 P 1.8 V for internal RAM and ROM

VDD1(FLASH1V8) V15 P 1.8 V for internal flash memory

VDD1(EMC) A16 P 1.8 V or 3.3 V for external memory controller

VDD1(IO3V3) E1 P 3.3 V for peripherals

VDD2(CORE1V8) V11 P 1.8 V for core

VDD2(EMC) A7 P 1.8 V or 3.3 V for external memory controller

VDD2(FLASH1V8) V16 P 1.8 V for internal flash memory

VDD2(IO3V3) V5 P 3.3 V for peripherals

VDD3(IO3V3) V14 P 3.3 V for peripherals

VDD4(IO3V3) J18 P 3.3 V for peripherals

VDD5(IO3V3) R1 P 3.3 V for peripherals

VDD6(IO3V3) R2 P 3.3 V for peripherals

VSS1(CORE) G1 P ground for internal RAM and ROM

VSS1(EMC) A15 P ground for external memory controller

VSS1(INT) T12 P ground for other internal blocks

VSS1(IO) F1 P ground for peripherals

VSS2(CORE) V12 P ground for core

VSS2(EMC) A6 P ground for external memory controller

VSS2(INT) U11 P ground for other internal blocks

VSS2(IO) V6 P ground for peripherals

VSS3(CORE) V17 P ground for core, substrate, flash

VSS3(INT) T11 P ground for other internal blocks

VSS3(IO) V13 P ground for peripherals

VSS4(IO) H18 P ground for peripherals

VSS5(IO) P2 P ground for peripherals

VSS6(IO) P1 P ground for peripherals

Table 4. Pin description

…continued

Symbol Ball # Type[1] Description

Preliminary data sheet Rev. 03 — 17 April 2008 12 of 43

NXP Semiconductors LPC2880; LPC2888

16/32-bit ARM microcontrollers with external memory interface

Lower speed peripheral functions are connected to the APBs. The four AHB-to-APB

bridges interface the APBs to the AHB.

6.1.1 ARM7TDMI processor

The ARM7TDMI is a general purpose 32-bit microprocessor that offers high performance

and very low power consumption. The ARM architecture is based on RISC principles, and

the instruction set and related decode mechanism are much simpler than those of

microprogrammed CISCs. This simplicity results in a high instruction throughput and

impressive real-time interrupt response from a small and cost-effective processor core.

Pipeline techniques are employed so that all parts of the processing and memory systems

can operate continuously. Typically, while one instruction is being executed, its successor

is being decoded, and a third instruction is being fetched from memory.

The ARM7TDMI processor also employs a unique architectural strategy known as Thumb,

which makes it ideally suited to high-volume applications with memory restrictions, or

applications where code density is an issue.

The key idea behind Thumb is that of a super-reduced instruction set. Essentially, the

ARM7TDMI processor has two instruction sets:

•The standard 32-bit ARM instruction set.

•A 16-bit Thumb instruction set.

The Thumb set’s 16-bit instruction length allows it to approach twice the density of

standard ARM code while retaining most of the ARM’s performance advantage over a

traditional 16-bit processor using 16-bit registers. This is possible because Thumb code

operates on the same 32-bit register set as ARM code.

Thumb code is able to provide down to 65 % of the code size of ARM, and 160 % of the

performance of an equivalent ARM processor connected to a 16-bit memory system.

The ARM7TDMI processor is described in detail on the ARM web site.

6.1.2 On-chip flash memory system

The LPC2880/2888 includes a 1 MB flash memory system. This memory may be used for

both code and data storage. Programming of the flash memory may be accomplished in

several ways. It may be programmed In System via the USB port. The application program

may also erase and/or program the flash while the application is running, allowing a great

degree of flexibility for data storage field firmware upgrades, etc.

The flash is 128 bit wide and includes buffering to allow 3 out of 4 sequential read

operations to operate without wait states.

6.1.3 On-chip SRAM

The LPC2880/2888 includes 64 kB of SRAM that may be used for code and/or data

storage.

6.1.4 On-chip ROM

The LPC2880/2888 includes an on-chip ROM that contains boot code. Execution begins

in on-chip ROM after a reset.

Preliminary data sheet Rev. 03 — 17 April 2008 13 of 43

NXP Semiconductors LPC2880; LPC2888

16/32-bit ARM microcontrollers with external memory interface

The boot code in this ROM reads the state of the mode inputs and accordingly does one

of the following:

•Starts execution in internal flash

•Starts execution in external memory

•Performs a hardware self-test, or

•Downloads code from the USB interface into on-chip RAM and transfers control to the

downloaded code

6.2 Memory map

The LPC2880/2888 memory map incorporates several distinct regions, as shown in

Figure 3. When an application is running, the CPU interrupt vectors are remapped to allow

them to reside in on-chip SRAM.

Preliminary data sheet Rev. 03 — 17 April 2008 14 of 43

NXP Semiconductors LPC2880; LPC2888

16/32-bit ARM microcontrollers with external memory interface

Fig 3. Memory map

remapped area

0x0000 0000

0.0 GB

2.0 GB

4.0 GB

0x0FFF FFFF

0x2000 0000

0x8000 0000

0x7FFF FFFF

0x1FFF FFFF

0xFFFF FFFF

0x1000 0000

internal memory

external memory

(first instance)

peripherals

static memory bank 2, 2 MB 0x2800 0000 to 0x281F FFFF

reserved 0x2420 0000 to 0x27FF FFFF

dynamic memory bank 0, 64 MB 0x3000 0000 to 0x33FF FFFF

exception vectors 0x0000 0000 to 0x0000 001F

static memory bank 1, 2 MB 0x2400 0000 to 0x241F FFFF

static memory bank 0, 2 MB 0x2000 0000 to 0x201F FFFF

reserved 0x1050 0000 to 0x1FFF FFFF

internal ROM (32 kB) 0x0020 0000 to 0x0020 7FFF

reserved 0x0050 0000 to 0x0FFF FFFF

internal RAM (64 kB) 0x0040 0000 to 0x0040 FFFF

reserved 0x2020 0000 to 0x23FF FFFF

internal flash (1 MB) 0x1040 0000 to 0x104F FFFF

reserved 0x1000 0000 to 0x0000 003F

reserved 0x2820 0000 to 0x2FFF FFFF

reserved 0x3400 0000 to 0x3FFF FFFF

static memory bank 2, 2 MB 0x4800 0000 to 0x481F FFFF

reserved 0x4420 0000 to 0x47FF FFFF

dynamic memory bank 0, 64 MB 0x5000 0000 to 0x53FF FFFF

static memory bank 1, 2 MB 0x4400 0000 to 0x441F FFFF

static memory bank 0, 2 MB 0x4000 0000 to 0x401F FFFF

reserved 0x4020 0000 to 0x43FF FFFF

reserved 0x4820 0000 to 0x4FFF FFFF

reserved 0x5400 0000 to 0x7FFF FFFF

0x4000 0000

0x3FFF FFFF

0x9000 0000

0x8FFF FFFF

external memory

(second instance)

1.0 GB

includes AHB and 4 APB buses 0x8000 0000 to 0x8FFF FFFF

reserved 0x9000 0000 to 0xFFFF FFFF

002aac240

Preliminary data sheet Rev. 03 — 17 April 2008 15 of 43

NXP Semiconductors LPC2880; LPC2888

16/32-bit ARM microcontrollers with external memory interface

6.3 Cache

The CPU of the LPC2880/2888 has been extended with a 2-way set-associative cache.

The cache is 8 kB in size and can store both data and instruction code.

If code that is being executed is present in the cache from a previous execution, the CPU

will not experience code fetch waits. Similarly, if requested data is present in the cache,

the CPU will not experience a data access wait.

The trade-off of introducing this cache is that each AHB access that bypasses the cache

will have an extra wait state inserted. Therefore it is advisable that both instruction caching

and data caching are turned on for most regions of on and off-chip memory.

6.3.1 Cache operation

The cache works as follows, for each page for which it is enabled:

•If data is read and is not in the cache (a cache miss), a line of eight 32-bit words is

read from the AHB bus. The CPU waits until this process is complete.

•If data is read and is found in the cache (a cache hit), data is read from cache with

zero wait states.

•If data is written, and the location is not in the cache (a cache miss), the data is written

directly to memory.

•If data is written, and the location is in the cache because this location has been read

before (a cache hit), the data is written into the cache with zero wait states, and the

cache line is marked as ‘dirty’.

•If a ‘dirty’ cache line is about to be discarded because of a cache miss (the cache line

needs to be reused for a different memory region), the old line is written back to

memory (a cache-line flush).

The cache can be set to data-only, instruction-only or combined (unified) caching. The

cache has 16 configurable pages, each 2 MB in range. The pages occupy the bottom

32 MB of the memory map. The virtual address and enable/disable status is configurable

for each page.

6.3.2 Features

•8 kB, 2-way set-associative cache.

•May be used as both an instruction and data cache.

•Zero wait states for a cache hit.

•16 configurable pages, each 2 MB in range.

6.4 Flash memory and programming

The LPC2888 incorporates 1 MB of flash memory, while the LPC2880 is a flash-less

device. The flash memory of the LPC2888 may be used for both code and data storage.

Programming of the flash memory may be accomplished in several ways. It may be

programmed In System via the USB port. The application program may also erase and/or

program the flash while the application is running, allowing a great degree of flexibility for

data storage, field firmware upgrades, etc.

Preliminary data sheet Rev. 03 — 17 April 2008 16 of 43

NXP Semiconductors LPC2880; LPC2888

16/32-bit ARM microcontrollers with external memory interface

Programming the flash in a running application is accomplished via a register interface on

the APB bus. The flash module can generate an interrupt request when burning or erasing

is completed.

The flash memory contains a buffer to allow for faster execution. Information is read from

the flash 128 bits at a time. The buffer holds this entire amount, which can represent four

32-bit ARM instructions. These captured instructions can them be executed without flash

read delays, improving system performance.

6.4.1 Features

•Flash access for processor execution and data read is via the AHB bus.

•Flash programming in a running application is via an APB register interface.

•Initial programming or reprogramming is can be accomplished from the USB port.

6.5 DC-to-DC converters

The LPC2880/2888 include two DC-to-DC converters providing an on-chip power system

which allows the device to be powered by a standard single cell battery (AA or AAA for

example) as well as receive power from a USB port or other power source.

The LPC2880/2888 need two supply voltages, 3.3 V and 1.8 V, for various internal

functions. When power is available from a higher voltage source such as USB, two

internal Low Dropout regulators (LDO regulators) reduce the incoming voltage to the level

needed by the LPC2880/2888. When only a low voltage battery supply is available, two

DC-to-DC converters boost the voltage up to the needed levels. Switching between the

two modes is supported.

6.6 External memory controller

The LPC2880/2888 External Memory Controller (EMC) is a multi-port memory controller

that supports asynchronous static memory devices such as RAM, ROM and flash, as well

as dynamic memories such as Single Data Rate SDRAM. It complies with ARM’s AMBA.

6.6.1 Features

•Dynamic memory interface support including single data rate SDRAM.

•Asynchronous static memory device support including RAM, ROM, and flash, with or

without asynchronous page mode.

•Low transaction latency.

•Read and write buffers to reduce latency and to improve performance.

•8-bit and 16-bit static memory support.

•16-bit SDRAM memory support.

•Static memory features include:

–Asynchronous page mode read.

–Programmable wait states.

–Bus turnaround delay.

–Output enable and write enable delays.

–Extended wait.

Preliminary data sheet Rev. 03 — 17 April 2008 17 of 43

NXP Semiconductors LPC2880; LPC2888

16/32-bit ARM microcontrollers with external memory interface

–2 MB address range with three chip selects.

•One chip select for synchronous memory and three chip selects for static memory

devices.

•Power-saving modes dynamically control CKE and CLKOUT to SDRAMs.

•Dynamic memory self-refresh mode controlled by software.

•Controller supports 2048, 4096, and 8192 row address synchronous memory parts.

That is typically 512 MB, 256 MB, and 128 MB parts, with 4, 8, or 16 data lines per

device.

Remark: Synchronous static memory devices (synchronous burst mode) are not

supported.

6.7 GPIO

Many device pins that are not needed for a specific peripheral function can be used as

GPIOs. These pins can be controlled by the mode registers. Pins may be dynamically

configured as inputs or outputs. Separate registers allow setting or clearing any number of

outputs simultaneously. The current state of the port pins may be read back via the PIN

registers.

6.7.1 Features

•81 pins have dual use as a specific function I/O or as a GPIO.

•Each dual use pin can be programmed for functional I/O, drive high, drive low, or

hi-Z/input.

•Four pins are dedicated as GPIO, programmable for drive high, drive low, or

hi-Z/input.

6.8 Interrupt controller

The interrupt controller accepts all of the interrupt request inputs and categorizes them as

FIQ or IRQ. The programmable assignment scheme means that priorities of interrupts

from the various peripherals can be dynamically assigned and adjusted.

FIQ has the highest priority. If more than one request is assigned to FIQ, the interrupt

controller combines the requests to produce the FIQ signal to the ARM processor.

The interrupt controller combines the requests from all the vectored IRQs to produce the

IRQ signal to the ARM processor. The IRQ service routine can start by reading a register

from the interrupt controller and jumping there.

6.8.1 Features

•Maps all LPC2880/2888 interrupt sources to processor FIQ and IRQ

•Level sensitive sources

•Programmable priority among sources

•Nested interrupt capability

•Software interrupt capability for each source

Preliminary data sheet Rev. 03 — 17 April 2008 18 of 43

NXP Semiconductors LPC2880; LPC2888

16/32-bit ARM microcontrollers with external memory interface

6.9 Event router

88 external and 11 internal LPC2880/2888 signals are connected to the Event Router

block. GPIO input pins, functional input pins, and even functional outputs can be

monitored by the Event Router.

Each signal can act as an interrupt source or a clock-enable for LPC2880/2888 modules,

with individual options for high- or low-level sensitivity or rising- or falling-edge sensitivity.

The outputs of the polarity and sensitivity logic can be read from Raw Status Registers 0

to 3.

Each active state is next masked/enabled by a “global” mask bit for that signal. The results

can be read from Pending Registers 0 to 3.

All 99 Pending signals are presented to each of the five output logic blocks. Each output

logic block includes a set of four Interrupt Output Mask Registers, each set totalling

99 bits, that control whether each signal applies to that output. These are logically ANDed

with the corresponding Pending signals, and the 99 results in each logic block are logically

ORed to make the output of the block. The 496 results can be read in the Interrupt Output

Pending Registers.

Outputs 0 to 3 are routed to the Interrupt Controller, in which each can be individually

enabled to cause an interrupt. Output 4 is routed to the Clock Generation Unit, in which it

can serve to enable clocking for selected clock domains. The five outputs can be read in

the Output Register.

6.10 General purpose timers

The LPC2880/2888 contains two fully independent general purpose timers. Each timer is

a 32 bit wide down counter with a selectable prescaler. The prescaler allows either the

system clock to be used directly, or the clock to be divided by 16 or 256.

Two modes of operation are available, free-running and periodic timer. In periodic timer

mode, the counter will generate an interrupt at a constant interval. In free-running mode

the timer will overflow after reaching its zero value and continue to count down from the

maximum value.

6.10.1 Features

•Two independent 32-bit timers.

•Free-running or periodic operating modes.

•Generate timed interrupts.

6.11 Watchdog timer

The purpose of the watchdog timer is to interrupt and/or reset the microcontroller within a

reasonable amount of time if it enters an erroneous state. When enabled, the watchdog

will generate an interrupt or a system reset if the user program fails to reset the watchdog

within a predetermined amount of time. Alternatively, it can be used as an additional

general purpose Timer.

Preliminary data sheet Rev. 03 — 17 April 2008 19 of 43

NXP Semiconductors LPC2880; LPC2888

16/32-bit ARM microcontrollers with external memory interface

The WDT clock increments a 32-bit Prescale Counter, the value of which is continually

compared to the value of the Prescale Register. When the Prescale Counter matches the

Prescale Register at a WDT clock edge, the Prescale Counter is cleared and the 32-bit

Timer Counter is incremented. Thus the Prescale facility divides the WDT clock by the

value in the Prescale Register plus one.

The value of the Timer Counter is continually compared to the values in two registers

called Match Register 0 and 1. When/if the value of the Timer Counter matches that of

Match Register 0 at a WDT clock edge, a signal ‘m0’ can be asserted to the Event Router,

which can be programmed to send an interrupt signal to the Interrupt Controller as a

result. When/if the value of the Timer Counter matches that of Match Register 1 at a WDT

clock edge, a signal ‘m1’ can be asserted to the CGU, which resets the chip as a result.

The CGU also includes a flag to indicate whether a reset is due to a watchdog time-out.

6.11.1 Features

•Optionally resets chip (via Clock Generation Unit) if not periodically reloaded.

•Optional interrupt via Event Router.

•32-bit Prescaler and 32-bit Counter allow extended watchdog period.

6.12 Real-time clock

The Real-time clock is a set of counters for measuring time when system power is on, and

optionally when it is off. It uses little power in either mode.

6.12.1 Features

•Measures the passage of time to maintain a calendar and clock.

•Ultra Low Power design to support battery powered systems.

•Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and Day

of Year.

•Dedicated 32 kHz oscillator.

•Dedicated power supply pin can be connected to a battery or to the main 1.8 V.

6.13 General purpose DMA controller

The General Purpose DMA controller (GPDMA) is an AMBA AHB compliant master

allowing selected LPC2880/2888 peripherals to have DMA support. Peripherals that can

be serviced by the GPDMA channels include the SD/MCI card interface, UART TX and/or

RX, the I2C-bus interface, the Simple Analog Out (SAO) front-ends to the I2S/DAO and

16-bit dual DACs, the Simple Analog In (SAI) interfaces for data from the I2S/DAI and

16-bit dual ADCs, and the LCD interface.

6.13.1 Features

•Eight DMA channels. Each channel can support a unidirectional transfer, or a pair of

channels can be used together to follow a linked list of buffer addresses and transfer

counts.

The GPDMA provides 16 peripheral DMA request lines. Most of these are connected

to the peripherals listed above; two can be used for external requests.

Preliminary data sheet Rev. 03 — 17 April 2008 20 of 43

NXP Semiconductors LPC2880; LPC2888

16/32-bit ARM microcontrollers with external memory interface

•The GPDMA supports a subset of the flow control signals supported by ARM DMA

channels, specifically ‘single’ but not ‘burst’ operation.

•Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and

peripheral-to-peripheral transfers.

•Scatter or gather DMA is supported through the use of linked lists. This means that

the source and destination areas do not have to occupy contiguous areas of memory.

•Rotating channel priority. Each DMA channel has equal opportunity to perform

transfers.

•The GPDMA is one of three AHB masters in the LPC2880/2888, the others being the

ARM7 processor and the USB interface.

•Incrementing or non-incrementing addressing for source and destination.

•Supports 8 bit, 16 bit, and 32 bit wide transactions.

•GPDMA channels can be programmed to swap data between big- and little-endian

formats during a transfer.

•An interrupt to the processor can be generated on DMA completion, when a DMA

channel is halfway to completion, or when a DMA error has occurred.

6.14 UART and IrDA

The LPC2880/2888 contains one UART with baud rate generator and IrDA support.

6.14.1 Features

•32-Byte Receive and Transmit FIFOs.

•Register locations conform to the 16C650 industry standard.

•Receiver FIFO trigger points at 1 B, 16 B, 24 B, and 28 B.

•Built-in baud rate generator.

•CGU generates UART clock including fractional divider capability.

•Auto baud capability.

•Optional hardware flow control.

•IrDA mode for infrared communication.

6.15 I2C-bus interface

The LPC2880/2888 I2C-bus interface is byte oriented and has four operating modes:

master Transmit mode, master Receive mode, slave Transmit mode and slave Receive

mode. The interface complies with the entire

C-bus specification

, and allows turning

power off to the LPC2880/2888 without causing a problem with other devices on the same

I2C-bus.

6.15.1 Features

•Standard I2C-bus interface, configurable as Master, Slave, or Master/Slave.

•Arbitration between simultaneously transmitting masters without corruption of serial

data on the bus.

•Programmable clock allows adjustment of I2C-bus transfer rates.

•Bidirectional data transfer between masters and slaves.

Preliminary data sheet Rev. 03 — 17 April 2008 21 of 43

NXP Semiconductors LPC2880; LPC2888

16/32-bit ARM microcontrollers with external memory interface

•Serial clock synchronization allows devices with different bit rates to communicate via

one serial bus.

•Serial clock synchronization can be used as a handshake mechanism to suspend and

resume serial transfer.

•Supports normal (100 kHz) and fast (400 kHz) operation.

6.16 10-bit ADC

The LPC2880/2888 contains a single 10-bit successive approximation ADC with five

multiplexed channels.

6.16.1 Features

•10-bit successive approximation ADC.

•Input multiplexing among 5 pins.

•Power-down mode.

•Measurement range 0 V to 3.3 V.

•10-bit conversion time ≥ 2.44 µs.

•Single or continuous conversion mode.

6.17 Analog I/O

The analog I/O system includes an I2S-bus input channel, an I2S-bus output channel, a

dual ADC, and a dual DAC. Each channel includes a separate 4-sample FIFO.

Each of the two ADC inputs is connected to a Programmable Gain Amplifier (PGA).

Each DAC has two output pins.

6.17.1 Features

•I2S-bus input channel with a 4-sample FIFO for stereo DAI.

•I2S-bus output channel with a 4-sample FIFO for stereo DAO.

•Dual 16-bit ADCs with individual inputs routed through programmable gain amplifiers.

Input takes place through a 4-sample FIFO.

•Dual 16-bit DACs. Each DAC has its own output pin. Output takes place through a

4-sample FIFO.

6.18 USB 2.0 Hi-Speed device controller

The USB is a 4-wire bus that supports communication between a host and a number (127

maximum) of peripherals. The host controller allocates the USB bandwidth to attached

devices through a token based protocol. The bus supports hot plugging, un-plugging and

dynamic configuration of the devices. All transactions are initiated by the host controller.

The host schedules transactions in 1 ms frames. Each frame contains an SOF marker and

transactions that transfer data to/from device endpoints. There are four types of transfers

defined for the endpoints. Control transfers are used to configure the device. Interrupt

transfers are used for periodic data transfer. Bulk transfers are used when rate of transfer

is not critical. Isochronous transfers have guaranteed delivery time but no error correction.

Preliminary data sheet Rev. 03 — 17 April 2008 22 of 43

NXP Semiconductors LPC2880; LPC2888

16/32-bit ARM microcontrollers with external memory interface

The LPC2880/2888 USB controller enables 480 Mbit/s or 12 Mbit/s data exchange with a

USB host controller. It includes a USB controller, a DMA engine, and a USB 2.0 ATX

physical interface.

The USB controller consists of the protocol engine and buffer management blocks. It

includes an SRAM that is accessible to the DMA engine and to the processor via the

The DMA engine is an AHB master, having direct access to all of ARM memory space but

particularly to on-chip RAM. Each USB endpoint that requires its data to be transferred via

DMA is allocated to a logical DMA channel in the DMA engine.

Endpoints with small packet sizes can be handled by software via registers in the USB

controller. In particular, Control Endpoint 0 is always handled in this way.

6.18.1 Features

•Fully compliant with

USB 2.0 specification

(Hi-Speed and Full-Speed).

•8 logical endpoints = 16 physical endpoints.

•Supports Control, Bulk, Interrupt and Isochronous endpoints.

•Endpoint type selection by software.

•Endpoint maximum packet size setting by software.

•Supports SoftConnect feature (requires an external 1.5 kΩ resistor between the

CONNECT pad and 3.3 V).

•Supports bus-powered capability with low suspend current.

•Two DMA channels, assignable to any of 4 physical endpoints.

•Supports Burst data transfers on the AHB.

•Supports Retry and Split transactions on the AHB.

6.19 SD/MMC card interface

The SD and MCI is an interface between the APB and multimedia and/or secure digital

memory cards.

The interface provides all functions specific to the Secure Digital/MultiMedia memory

card, such as the clock generation unit, power management control, command, data

transfer, interrupt generation, and DMA request generation.

6.19.1 Features

•Conformance to

Multimedia Card Specification v2.11

•Conformance to

Secure Digital Memory Card Physical Layer Specification, v0.96

•Use as a multimedia card bus or a secure digital memory card bus host. It can be

connected to several multimedia cards, or a single secure digital memory card.

•DMA transfers are supported through the Simple DMA facility.

Preliminary data sheet Rev. 03 — 17 April 2008 23 of 43

NXP Semiconductors LPC2880; LPC2888

16/32-bit ARM microcontrollers with external memory interface

6.20 LCD interface

The LCD interface contains logic to interface to a 6800 or 8080 bus compatible LCD

controller. The LCD interface is compatible with the 6800 bus standard and the 8080 bus

standard, with one address pin (RS) for selecting the data or instruction register.

The LCD interface makes use of a configurable clock (programmed in the CGU) to adjust

the speed of the 6800/8080 bus to the speed of the connected peripheral.

6.20.1 Features

•8-bit or 4-bit parallel interface mode: 6800-series, 8080-series.

•Selectable bus frequency supports high and low speed LCD controllers.

•Supports polling the busy flag from the LCD controller to avoid CPU polling.

•Contains a 16 B FIFO for sending control and data information to the LCD controller.

•Contains a serial interface which uses the same FIFO for serial transmissions.

•Supports FIFO level flow control to the General Purpose DMA controller.

6.21 Clocking and power control

Clocking in the LPC2880/2888 is controlled by a versatile CGU, so that system and

peripheral requirements may be met while allowing optimization of power consumption.

Clocks to most functions may be turned off if not needed, and may be enabled and

disabled by selected events through the Event Router.

Clock sources include a high frequency (1 MHz to 20 MHz) crystal oscillator and a 32 kHz

RTC oscillator. Higher frequency clocks may be generated through the use of two

programmable PLLs.

Reset of individual functional blocks is also controlled by the CGU. Full chip reset can be

initiated by the external reset pin or by the watchdog timer.

6.21.1 Features

•Power and performance control provided by versatile clock generation to individual

functional blocks.

•Multiple clock sources including external crystal and programmable PLLs.

•Individual control of software reset to many functional blocks.

6.21.2 Reset

The LPC2880/2888 has two sources of reset: the RESET pin and the watchdog reset. The

RESET pin includes an on-chip pull-up. RESET must remain low at power-up for 1 ms

after power supply voltages are stable. This includes on-chip DC-to-DC converter

voltages.

When either reset is removed, the processor begins executing at address 0, which is the

reset vector. At that point, all of the processor and peripheral registers have been

initialized to predetermined values.

Preliminary data sheet Rev. 03 — 17 April 2008 24 of 43

NXP Semiconductors LPC2880; LPC2888

16/32-bit ARM microcontrollers with external memory interface

The on-chip watchdog timer can cause a chip reset if not updated within a programmable

time interval. A status register allows software to determine if a reset was caused by the

watchdog timer. The watchdog timer can also be configured to generate an interrupt if

desired.

Software reset of many individual functional blocks may be performed via registers within

the CGU.

6.21.3 Crystal oscillator

The main oscillator is the basis for the clocks most chip functions use by default. The

oscillator may be used with crystal frequencies from 1 MHz to 20 MHz.

6.21.4 PLLs

The LPC2880/2888 includes two PLLs: the main PLL provides clocks to most chip

functions, and a high-speed PLL that can be used to generate faster clocks for selected

chip functions. Each PLL can be driven from several clock sources. These include the

main oscillator (1 MHz to 20 MHz), the RTC oscillator (32 kHz), the bit clock or word

select inputs of the I2S input channel, the clock input from the SD/MMC card interface, or

the output clock from the other PLL.

The low power PLL takes the input clock and multiplies it up to a higher frequency (by 1 to

32), then divides it down (by 1, 2, 4, or 8) to provide the output clock used by the CGU.

The output frequency of this PLL can range from 10 MHz to 320 MHz. Functional blocks

may have limitations below this upper limit.

The high-speed PLL takes the input clock, optionally divides it down (by 1 to 256), then

multiplies it up to a higher frequency (by 1 to 1024), then divides it down (by 1 to 16) to

provide the output clock used by the CGU. The output frequency of this PLL can range

from 4.3 MHz to 550 MHz. Functional blocks may have limitations below this upper limit.

6.21.5 Power control and modes

Power control on the LPC2880/2888 is accomplished by detailed control over the clocking

of each functional block via the CGU. The LPC2880/2888 includes a very versatile

clocking scheme that provides a great deal of control over performance and power usage.

On-chip functions are divided into 11 groups. Each group has a selection for one of

several basic clock sources. Graceful (glitch-free) switching between these clock sources

is provided.

Three of these functional groups include one fractional divider that allows any rate below

the selected clock to be derived. Three other functional groups include more than one

fractional divider, allowing several different slower clocks to be generated within the group.

Each function within the group can then be assigned to use any one of the generated

clocks.

Each function within any group can also be individually turned off by disabling the clock to

that function. When added to the versatile clock rate selection, this allows very detailed

control of power utilization.

Each function also can be configured to have clocks automatically turned on and off

based on a signal from the Event Router.

Preliminary data sheet Rev. 03 — 17 April 2008 25 of 43

NXP Semiconductors LPC2880; LPC2888

16/32-bit ARM microcontrollers with external memory interface

6.21.6 APBs

Most peripheral functions are accessed by on-chip APBs that are attached to the higher

speed AHB. The APBs perform reads and writes to peripheral registers in three peripheral

clocks.

6.22 Emulation and debugging

The LPC2880/2888 supports emulation via a dedicated JTAG serial port. The dedicated

JTAG port allows debugging of all chip features without impact to any pins that may be

used in the application.

Standard ARM EmbeddedICE logic provides on-chip debug support. The debugging of

the target system requires a host computer running the debugger software and an

EmbeddedICE protocol converter. The EmbeddedICE protocol converter converts the

Remote Debug Protocol commands to the JTAG data needed to access the ARM core.

In accordance with the Absolute Maximum Rating System (IEC 60134;,

Preliminary data sheet Rev. 03 — 17 April 2008 26 of 43

NXP Semiconductors LPC2880; LPC2888

16/32-bit ARM microcontrollers with external memory interface

7. Limiting values

[1] The following applies to Table 5:

a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive

static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum.

b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless

otherwise noted.

[2] All inputs are 5 V tolerant except external memory bus and USB pins.

[3] Referenced to the applicable VDD for the pin. Not to exceed 4.6 V.

[4] Including voltage on outputs in 3-state mode.

[5] Based on package heat transfer, not device power consumption.

[6] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor.

Table 5. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

[1]

Symbol Parameter Conditions Min Max Unit

VDD(1V8) supply voltage (1.8 V) −0.5 +1.95 V

VDD(3V3) supply voltage (3.3 V) −0.5 +4.6 V

VDD(EMC) external memory controller

supply voltage in 1.8 V range −0.5 +1.95 V

in 3.3 V range −0.5 +3.6 V

VIA analog input voltage −0.5 VDD(ADC3V3) V

VIinput voltage 5 V tolerant pins [2][4] −0.5 +6.0 V

input voltage other pins [2][3][4] −0.5 VDD + 0.5 V

IDD supply current per supply pin - 100 mA

ISS ground current per ground pin - 100 mA

Tstg storage temperature −40 +125 °C

Ptot(pack) total power dissipation (per

package)

[5] - 1.5 W

Vesd electrostatic discharge voltage human body model [6]

all pins −1000 +1000 V

'ML

Preliminary data sheet Rev. 03 — 17 April 2008 27 of 43

NXP Semiconductors LPC2880; LPC2888

16/32-bit ARM microcontrollers with external memory interface

8. Static characteristics

Table 6. Static characteristics

amb

−

C to +85

C, unless otherwise specified.

Symbol Parameter Conditions Min Typ[1] Max Unit

VDD(1V8) supply voltage (1.8 V) [2] 1.7 1.8 1.95 V

VDD(3V3) supply voltage (3.3 V) [3] 3 3.3 3.6 V

VDDA(3V3) analog supply voltage (3.3 V) [4] 3 3.3 3.6 V

VDD(EMC) external memory controller

supply voltage in 1.8 V range [5] 1.7 1.8 1.95 V

in 3.3 V range [5] 2.7 3.3 3.6 V

Standard pins

IIL LOW-level input current VI = 0 V; no pull-up - - 1 µA

IIH HIGH-level input current VI = VDD; no pull-down [6] --1µA

IOZ OFF-state output current VO = 0 V; VO=V

DD; no

pull-up/down

[6] --1µA

Vhys(i) input hysteresis voltage 300 - - mV

Ilatch I/O latch-up current −(1.5VDD) < VI < (1.5VDD)[6] - - 100 mA

VIinput voltage [6][7] 0-V

DD V

[6][7][10] 0 - 5.5 V

VIH HIGH-level input voltage [8] 1.6 - - V

[9] 2.0 - - V

VIL LOW-level input voltage [8] - - 0.6 V

[9] - - 0.8 V

VOH HIGH-level output voltage IOH = −1mA [8][11] VDD − 0.4 - - V

IOH = −4mA [9][11] VDD − 0.4 - - V

VOL LOW-level output voltage IOL = 4 mA [8][11] - - 0.4 V

IOL = 4 mA [9][11] - - 0.4 V

IOH HIGH-level output current VOH = VDD − 0.4 V [6][11] -−4-mA

IOL LOW-level output current VOL = 0.4 V [6][11] -4-mA

IOHS HIGH-level short-circuit output

current VOH = 0 V [12] -−45 - mA

IOLS LOW-level short-circuit output

current VOL = VDD [6][12] -50-mA

Ipu pull-up current VI = 0 V [6] −13 −36 −50 µA

VDD < VI < 5.5 V [6][10] -0-µA

Ipd pull-down current VI = VDD [6] 20 50 75 µA

I2C-bus pins

VIH HIGH-level input voltage 3.5 - - V

VIL LOW-level input voltage - - 1.5 V

Vhys(i) input hysteresis voltage 250 - - mV

VOL LOW-level output voltage IOL = 3 mA - - 0.4 V

ILI input leakage current VI=V

DD [6] -24µA

VI = 5 V - 10 22 µA

Preliminary data sheet Rev. 03 — 17 April 2008 28 of 43

NXP Semiconductors LPC2880; LPC2888

16/32-bit ARM microcontrollers with external memory interface

Oscillator pins

Vi(xtal) crystal input voltage on pins XTALI and X32I 0 - 1.8 V

Vo(xtal) crystal output voltage on pins XTALO and X32O 0 - 1.8 V

DC-to-DC converter

VBAT battery supply voltage 0.9 1.2 1.6 V

VO(DCDC1) DC-to-DC converter 1 output

voltage VBAT = 1.2 V;

IL(DCDC1)(max) = 100 mA - 3.2 - V

IL(DCDC1)(max) maximum DC-to-DC converter

1 load current - 100 - mA

fi(clk)(DCDC1) DC-to-DC converter 1 clock

input frequency - 12 - MHz

VO(DCDC2) DC-to-DC converter 2 output

voltage VBAT = 1.2 V;

IL(DCDC2)(max) =90mA - 1.83 - V

IL(DCDC2)(max) maximum DC-to-DC converter

2 load current -90-mA

fi(clk)(DCDC2) DC-to-DC converter 2 clock

input frequency - 12 - MHz

VUSB USB supply voltage 4.0 5.0 5.5 V

VO(LDO1) LDO1 output voltage VUSB = 5.0 V;

IL(LDO1)(max) = 150 mA - 3.4 - V

IL(LDO1)(max) maximum LDO1 load current - 150 - mA

VO(LDO2) LDO2 output voltage VUSB = 5.0 V;

IL(LDO2)(max) = 100 mA - 1.88 - V

IL(LDO2)(max) maximum LDO2 load current - 100 - mA

Power consumption

IDD(CORE) core supply current VDD = 1.8 V [13] -60-mA

IDD(EMC) external memory controller

supply current VDD(EMC) = 1.8 V;

HCLK = 18 MHz

[14] - 1.2 - mA

VDD(EMC) = 3.3 V;

HCLK = 36 MHz

[14] - 2.2 - mA

IBAT battery supply current VDCDC_VBAT = 1.2 V - 130 - mA

powered down - 18 - µA

ICC(osc) oscillator supply current oscillator running [15] - 300 - µA

oscillator powered down [15] --10µA

IDD(RTC) RTC supply current oscillator running [16] - 300 - µA

oscillator powered down [16] --10µA

IDD(ADC) ADC supply current normal [17] - - 400 µA

powered down [17] - - < 1 µA

IDDIA analog input supply current normal [18] -6-mA

powered down [18] -10-µA

IDDO(DAC) DAC output supply current normal [19] - 0.7 - mA

powered down [19] -10-µA

Table 6. Static characteristics

…continued

amb

−

C to +85

C, unless otherwise specified.

Symbol Parameter Conditions Min Typ[1] Max Unit

Typ,

Preliminary data sheet Rev. 03 — 17 April 2008 29 of 43

NXP Semiconductors LPC2880; LPC2888

16/32-bit ARM microcontrollers with external memory interface

Power consumption (battery supplies voltage)

IBAT battery supply current stop mode [20] - 17.7 - µA

Power consumption (DC-to-DC converter supplies voltage)

IDD supply current 32.768 kHz oscillator runs;

12 MHz oscillator stops;

DC-to-DC converter

supplies 1.8 V

[20] - 0.20 - mA

IDD supply current 32.768 kHz oscillator stops;

12 MHz oscillator runs;

DC-to-DC converter

supplies 1.8 V

[20] - 0.99 - mA

IDD supply current 32.768 kHz oscillator runs;

12 MHz oscillator stops;

DC-to-DC converter

supplies 3.3 V

[20] - 0.79 - mA

IDD supply current 32.768 kHz oscillator stops;

12 MHz oscillator runs;

DC-to-DC converter

supplies 3.3 V

[20] - 0.79 - mA

Power consumption (LDO regulator supplies voltage)

IDD supply current 32.768 kHz oscillator runs;

12 MHz oscillator stops;

LDO regulator supplies

1.8 V

[20] - 1.61 - mA

IDD supply current 32.768 kHz oscillator stops;

12 MHz oscillator runs; LDO

regulator supplies 1.8 V

[20] - 2.47 - mA

IDD supply current 32.768 kHz oscillator runs;

12 MHz oscillator stops;

LDO regulator supplies

3.3 V

[20] - 3.12 - mA

IDD supply current 32.768 kHz oscillator stops;

12 MHz oscillator runs; LDO

regulator supplies 3.3 V

[20] - 3.12 - mA

Power consumption (external DC-to-DC converter supplies voltage)

IDD supply current 32.768 kHz oscillator runs;

12 MHz oscillator stops;

external DC-to-DC

converter supplies 1.8 V

[20] - 0.20 - mA

Table 6. Static characteristics

…continued

amb

−

C to +85

C, unless otherwise specified.

Symbol Parameter Conditions Min Typ[1] Max Unit

Typ,

Preliminary data sheet Rev. 03 — 17 April 2008 30 of 43

NXP Semiconductors LPC2880; LPC2888

16/32-bit ARM microcontrollers with external memory interface

[1] Typical ratings are not guaranteed. The values listed are at room temperature (+25 ˚C), nominal supply voltages.

[2] Applies to pins VDD1(CORE1V8), VDD2(CORE1V8), VDD(DADC1V8), VDD1(FLASH1V8), VDD2(FLASH1V8), VDD(OSC1V8), VDD(OSC321V8), VDD1(USB1V8),

VDD2(USB1V8).

[3] External supply voltage; applies to pins VDD3(USB3V3), VDD4(USB3V3), VDD1(IO3V3), VDD2(IO3V3), VDD3(IO3V3), VDD4(IO3V3).

[4] Applies to pins VDD(DADC3V3), VDD(ADC3V3), VDD(DAC3V3), VDD5(IO3V3), VDD6(IO3V3).

[5] External supply voltage; applies to pins VDD1(EMC), VDD2(EMC).

[6] Referenced to the applicable VDD for the pin, which must be present.

[7] Including voltage on outputs in 3-state mode.

[8] Applies to pins with a VDD supply of 1.8 V.

[9] Applies to pins with a VDD supply of 3.3 V.

[10] Applies to 5 V tolerant pins.

[11] Accounts for 100 mV voltage drop in all supply lines.

[12] Only allowed for a short time period.

[13] Applies to pins VDD1(CORE1V8), VDD2(CORE1V8), VDD1(FLASH1V8), VDD2(FLASH1V8)

[14] Applies to pins VDD1(EMC), VDD2(EMC).

[15] Applies to pin VDD(OSC1V8).

[16] Applies to pin VDD(OSC321V8).

[17] Applies to pin VDD(ADC3V3).

[18] Applies to pins VDD(DADC1V8), VDD(DADC3V3).

[19] Applies to pin VDD(DAC3V3).

[20] All the above tests were done on the Icetech LPC288x evaluation board. Here are the different configurations that need to be done to

achieve the above numbers:

a) Resistors R7 and R8 on the board should be removed to reduce the power consumption on the LED’s D2 and D3.

b) The Analog-to-Digital Converter (ADC), the Dual-channel 16-bit Analog-to-Digital Converter and the Dual-channel 16-bit

Digital-to-Analog Converter are powered down.

c) The USB device controller is suspended.

d) All power control registers in the Clock Generation Unit have a value of 7h, and the Power Mode register in the Clock Generation Unit

has a value of 3h such that the output clocks of all spreading stages are disabled.

e) The floating pins are set to output state.

f) The Event Router is configured in such a way that it will generate its wake-up output to the Clock Generation Unit with a rising-edge

signal on the MODE1/P2[2] or the MODE2/P2[3].

IDD supply current 32.768 kHz oscillator stops;

12 MHz oscillator runs;

external DC-to-DC

converter supplies 1.8 V

[20] - 0.97 - mA

IDD supply current 32.768 kHz oscillator runs;

12 MHz oscillator stops;

external DC-to-DC

converter supplies 3.3 V

[20] - 1.27 - mA

IDD supply current 32.768 kHz oscillator stops;

12 MHz oscillator runs;

external DC-to-DC

converter supplies 3.3 V

[20] - 1.27 - mA

Table 6. Static characteristics

…continued

amb

−

C to +85

C, unless otherwise specified.

Symbol Parameter Conditions Min Typ[1] Max Unit

“C, unless olhelwise speciﬁed,

Preliminary data sheet Rev. 03 — 17 April 2008 31 of 43

NXP Semiconductors LPC2880; LPC2888

16/32-bit ARM microcontrollers with external memory interface

9. Dynamic characteristics

[1] Parameters are valid over operating temperature range unless otherwise specified.

[2] Supplied by an external crystal.

Table 7. Dynamic characteristics

amb

−

C to +85

C, unless otherwise specified.

[1]

Symbol Parameter Conditions Min Typ Max Unit

External clock

fext external clock frequency [2] 1 12 20 MHz

Port pins

trrise time - 5 - ns

tffall time - 5 - ns

Preliminary data sheet Rev. 03 — 17 April 2008 32 of 43

NXP Semiconductors LPC2880; LPC2888

16/32-bit ARM microcontrollers with external memory interface

[1] Refer to the

LPC2800 user manual UM10208_2

for the programming of WAITOEN and HCLK.

[2] Refer to the

LPC2800 user manual UM10208_2

for the programming of WAITRD and HCLK.

[3] (WAITRD −WAITOEN + 1) = 3 min at 60 MHz.

[4] Refer to the

LPC2800 user manual UM10208_2

for the programming of WAITWEN and HCLK.

[5] Refer to the

LPC2800 user manual UM10208_2

for the programming of WAITWR and HCLK.

[6] (WAITWD −WAITWEN + 1) = 3 min at 60 MHz.

Table 8. Dynamic characteristics: static external memory interface

=25pF, T

amb

=20

C, V

DD1(EMC)

DD2(EMC)

= 3.3 V and 1.8 V.

Symbol Parameter Conditions Min Typ Max Unit

Common to read and write cycles

tCSLAV CS LOW to address valid

time -0 - ns

Read cycle parameters

tOELAV OE LOW to address valid

time

[1] -0−WAITOEN ×HCLK - ns

tBLSLAV BLS LOW to address valid

time

[1] -0−WAITOEN ×HCLK - ns

tCSLOEL CS LOW to OE LOW time - 0 + WAITOEN ×HCLK - ns

tCSLBLSL CS LOW to BLS LOW time [1] - 0 + WAITOEN ×HCLK - ns

tOELOEH OE LOW to OE HIGH time [1][2][3] - (WAITRD −WAITOEN + 1) ×HCLK - ns

tBLSLBLSH BLS LOW to BLS HIGH time [1][2][3] - (WAITRD −WAITOEN + 1) ×HCLK - ns

tsu(DQ) data input/output set-up time - 33.3 - ns

th(DQ) data input/output hold time - 0 - ns

tCSHOEH CS HIGH to OE HIGH time - 0 - ns

tCSHBLSH CS HIGH to BLS HIGH time - 0 - ns

tOEHANV OE HIGH to address invalid

time -2×HCLK - ns

tBLSHANV BLS HIGH to address invalid

time -2×HCLK - ns

Write cycle parameters

tCSLDV CS LOW to data valid time - 0 - ns

tCSLWEL CS LOW to WE LOW time [4] - (WAITWEN + 1) ×HCLK - ns

tCSLBLSL CS LOW to BLS LOW time [4] - WAITWEN ×HCLK - ns

tWELDV WE LOW to data valid time [4] -0−(WAITWEN + 1) ×HCLK - ns

tWELWEH WE LOW to WE HIGH time [4][5][6] - (WAITWR −WAITWEN + 1) ×HCLK - ns

tBLSLBLSH BLS LOW to BLS HIGH time [4][5] - (WAITWR −WAITWEN + 3) ×HCLK - ns

tWEHANV WE HIGH to address invalid

time -1×HCLK - ns

tWEHDNV WE HIGH to data invalid time - 1 ×HCLK - ns

tBLSHANV BLS HIGH to address invalid

time -0 - ns

tBLSHDNV BLS HIGH to data invalid

time -0 - ns

ers,

Preliminary data sheet Rev. 03 — 17 April 2008 33 of 43

NXP Semiconductors LPC2880; LPC2888

16/32-bit ARM microcontrollers with external memory interface

[1] CKE is HIGH during the read cycle.

[2] CKE is HIGH during the write cycle

Table 9. Dynamic characteristics: dynamic external memory interface

=25pF, T

amb

=20

C, V

DD1(EMC)

DD2(EMC)

= 3.3 V.

Symbol Parameter Conditions Min Typ Max Unit

Read cycle parameters[1]

tCHCX clock HIGH time - 11.1 - ns

tCLCX clock LOW time - 11.1 - ns

TCLCL clock cycle time - 27.8 - ns

tsu(S) chip select set-up time - 7.5 - ns

th(S) chip select hold time - 3.5 - ns

tsu(RAS) row address strobe set-up time - 7.5 - ns

th(RAS) row address strobe hold time - 3.5 - ns

tsu(CAS) column address strobe set-up

time - 7.5 - ns

th(CAS) column address strobe hold time - 3.5 - ns

tsu(G) output enable set-up time - 7.5 - ns

th(G) output enable hold time - 3.5 - ns

tsu(A) address set-up time - 7.5 - ns

th(A) address hold time - 3.5 - ns

tsu(DQ) data input/output set-up time - 23.5 - ns

th(DQ) data input/output hold time - 3.5 - ns

Write cycle parameters[2]

tCHCX clock HIGH time - 11.1 - ns

tCLCX clock LOW time - 11.1 - ns

TCLCL clock cycle time - 27.8 - ns

tsu(S) chip select set-up time - 7.5 - ns

th(S) chip select hold time - 3.5 - ns

tsu(RAS) row address strobe set-up time - 7.5 - ns

th(RAS) row address strobe hold time - 3.5 - ns

tsu(CAS) column address strobe set-up

time - 7.5 - ns

th(CAS) column address strobe hold time - 3.5 - ns

tsu(W) write set-up time - 7.5 - ns

th(W) write hold time - 3.5 - ns

tsu(DQM) DQM set-up time - 7.5 - ns

th(DQM) DQM hold time - 3.5 - ns

tsu(A) address set-up time - 7.5 - ns

th(A) address hold time - 3.5 - ns

tsu(DQ) data input/output set-up time - 16.5 - ns

th(DQ) data input/output hold time - 10.5 - ns

ers,

Preliminary data sheet Rev. 03 — 17 April 2008 34 of 43

NXP Semiconductors LPC2880; LPC2888

16/32-bit ARM microcontrollers with external memory interface

[1] CKE is HIGH during the read cycle.

[2] CKE is HIGH during the write cycle.

Table 10. Dynamic characteristics: dynamic external memory interface

=25pF, T

amb

=20

C, V

DD1(EMC)

DD2(EMC)

= 1.8 V.

Symbol Parameter Conditions Min Typ Max Unit

Read cycle parameters[1]

tCHCX clock HIGH time - 23 - ns

tCLCX clock LOW time - 23 - ns

TCLCL clock cycle time - 55.6 - ns

tsu(S) chip select set-up time - 40 - ns

th(S) chip select hold time - 3.5 - ns

tsu(RAS) row address strobe set-up time - 40 - ns

th(RAS) row address strobe hold time - 3.5 - ns

tsu(CAS) column address strobe set-up

time -40 - ns

th(CAS) column address strobe hold time - 3.5 - ns

tsu(G) output enable set-up time - 40 - ns

th(G) output enable hold time - 3.5 - ns

tsu(A) address set-up time - 36 - ns

th(A) address hold time - 19.5 - ns

tsu(DQ) data input/output set-up time - 51.5 - ns

th(DQ) data input/output hold time - 4 - ns

Write cycle parameters[2]

tCHCX clock HIGH time - 23 - ns

tCLCX clock LOW time - 23 - ns

TCLCL clock cycle time - 55.6 - ns

tsu(S) chip select set-up time - 40 - ns

th(S) chip select hold time - 3.5 - ns

tsu(RAS) row address strobe set-up time - 40 - ns

th(RAS) row address strobe hold time - 3.5 - ns

tsu(CAS) column address strobe set-up

time -40 - ns

th(CAS) column address strobe hold time - 3.5 - ns

tsu(W) write set-up time - 40 - ns

th(W) write hold time - 3.5 - ns

tsu(DQM) DQM set-up time - 40 - ns

th(DQM) DQM hold time - 3.5 - ns

tsu(A) address set-up time - 36 - ns

th(A) address hold time - 19.5 - ns

tsu(DQ) data input/output set-up time - 31 - ns

th(DQ) data input/output hold time - 24.5 - ns

Preliminary data sheet Rev. 03 — 17 April 2008 35 of 43

NXP Semiconductors LPC2880; LPC2888

16/32-bit ARM microcontrollers with external memory interface

9.1 Timing

Fig 4. External memory read access to static memory

tCSHOEH

tCSHBLSH

tOEHANV

tBLSHANV

tCSLOEL

tOELOEH

tCSLBLSL

tBLSLBLSH

tCSLAV

tOELAV

tBLSLAV

th(DQ)

tsu(DQ)

STCS

BLS

002aac966

Preliminary data sheet Rev. 03 — 17 April 2008 36 of 43

NXP Semiconductors LPC2880; LPC2888

16/32-bit ARM microcontrollers with external memory interface

Fig 5. External memory write access to static memory

tBLSLBLSH

tCSLAV

tCSLDV tWEHANV

tCSLWEL

tCSLBLSL

tWEHDNV

tBLSHDNV

tBLSHANV

tWELWEH

tWELDV

STCS

BLS

002aac974

y; W

Preliminary data sheet Rev. 03 — 17 April 2008 37 of 43

NXP Semiconductors LPC2880; LPC2888

16/32-bit ARM microcontrollers with external memory interface

Fig 6. External memory read access to dynamic memory

th(A)

th(DQ)

tsu(RAS)

tsu(A)

tsu(DQ)

RAS

CAS, DQM

002aac975

CLK

TCLCL tCHCX

tCLCX

th(RAS)

DYCS

tsu(CAS), tsu(G)

th(CAS), th(G)

tsu(S)

th(S)

%¥; TM

Preliminary data sheet Rev. 03 — 17 April 2008 38 of 43

NXP Semiconductors LPC2880; LPC2888

16/32-bit ARM microcontrollers with external memory interface

Fig 7. External memory write access to dynamic memory

002aac976

th(A)

th(DQ)

tsu(RAS)

tsu(A)

tsu(DQ)

RAS

CAS, DQM

CLK

TCLCL tCHCX

tCLCX

th(RAS)

DYCS

tsu(CAS), tsu(DQM)

th(CAS), th(DQM)

tsu(W)

th(W)

tsu(S)

th(S)

D + Cl E:E}€§ mam» 000 one one one one Doe, 000 000 000 000 000 k¢oo one one 000 k¢oo k¢oo 000000000 000000000 000000000 oooooo oooooo oooooo oooooooouooooooooo oooooooooooooooooo ooooooooooooooooo

Preliminary data sheet Rev. 03 — 17 April 2008 39 of 43

NXP Semiconductors LPC2880; LPC2888

16/32-bit ARM microcontrollers with external memory interface

10. Package outline

Fig 8. Package outline SOT640-1 (TFBGA180)

0.5

A1bA2

UNIT Dy

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

01-06-07

03-03-03

IEC JEDEC JEITA

mm 1.11 0.31

0.19 0.84

0.76 10.1

9.9

10.1

9.9

0.39

0.29 0.12 0.1

8.5

DIMENSIONS (mm are the original dimensions)

SOT640-1 MO-195

0.1

0.15

0 2.5 5 mm

scale

SOT640-1

TFBGA180: plastic thin fine-pitch ball grid array package; 180 balls; body 10 x 10 x 0.8 mm

max.

AA2

A1detail X

y1C

2468

910

1357

ball A1

index area

ball A1

index area

∅ vM

∅ wM

1/2 e

Preliminary data sheet Rev. 03 — 17 April 2008 40 of 43

NXP Semiconductors LPC2880; LPC2888

16/32-bit ARM microcontrollers with external memory interface

11. Abbreviations

Table 11. Acronym list

Acronym Description

ADC Analog-to-Digital Converter

AMBA Advanced Microcontroller Bus Architecture

AHB Advanced High-performance Bus

APB Advanced Peripheral Bus

CISC Complex Instruction Set Computer

CGU Clock Generation Unit

DAC Digital-to-Analog Converter

DMA Direct Memory Access

DAI Digital Audio Input

DAO Digital Audio Output

FIQ Fast Interrupt Request

GPIO General Purpose Input/Output

IrDA Infrared Data Association

IRQ Interrupt Request

JTAG Joint Test Action Group

LCD Liquid Crystal Display

MCI Multimedia Card Interface

PLL Phase-Locked Loop

RISC Reduced Instruction Set Computer

SD Secure Digital

SD/MMC Secure Digital/MultiMedia Card

SDRAM Synchronous Dynamic Random Access Memory

SOF Start Of Frame

SRAM Static Random Access Memory

UART Universal Asynchronous Receiver/Transmitter

USB Universal Serial Bus

WDT WatchDog Timer

Preliminary data sheet Rev. 03 — 17 April 2008 41 of 43

NXP Semiconductors LPC2880; LPC2888

16/32-bit ARM microcontrollers with external memory interface

12. Revision history

Table 12. Revision history

Document ID Release date Data sheet status Change notice Supersedes

LPC2880_LPC2888_3 20080417 Preliminary data sheet - LPC2880_2888_2

Modifications: •Table 1 “Ordering information”; added /01 and /D1 parts.

•Table 2 “Ordering options”; added JTAG interface column to show the difference between

/01 and /D1 devices.

•Table 5; ESD specification added.

•Table 6; DC-to-DC converter and power consumption characteristics added.

•Table 8,Table 9,Table 10; external memory interface dynamic characteristics added.

•Figure 1, changed ‘ARM7TDMI-S’ to ‘ARM7TDMI’.

•Figure 4,Figure 5,Figure 6,Figure 7; external memory interface timing diagrams added.

LPC2880_LPC2888_2 20061121 Preliminary data sheet - LPC2880_LPC2888_1

LPC2880_LPC2888_1 20060622 Preliminary data sheet - -

Preliminary data sheet Rev. 03 — 17 April 2008 42 of 43

NXP Semiconductors LPC2880; LPC2888

16/32-bit ARM microcontrollers with external memory interface

13. Legal information

13.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

13.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

13.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/profile/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conflict between information in this document and such

terms and conditions, the latter will prevail.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

13.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

I2C-bus — logo is a trademark of NXP B.V.

SoftConnect — is a trademark of NXP B.V.

14. Contact information

For additional information, please visit: http://www.nxp.com

For sales office addresses, send an email to: salesaddresses@nxp.com

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data from the objective specification for product development.

Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.

Product [short] data sheet Production This document contains the product specification.

founded by PHILIPS

NXP Semiconductors LPC2880; LPC2888

16/32-bit ARM microcontrollers with external memory interface

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 17 April 2008

Document identifier: LPC2880_LPC2888_3

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

15. Contents

1 General description . . . . . . . . . . . . . . . . . . . . . . 1

2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2.1 Key features . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2

3.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2

4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6

6 Functional description . . . . . . . . . . . . . . . . . . 11

6.1 Architectural overview. . . . . . . . . . . . . . . . . . . 11

6.1.1 ARM7TDMI processor . . . . . . . . . . . . . . . . . . 12

6.1.2 On-chip flash memory system . . . . . . . . . . . . 12

6.1.3 On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 12

6.1.4 On-chip ROM . . . . . . . . . . . . . . . . . . . . . . . . . 12

6.2 Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 13

6.3 Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6.3.1 Cache operation . . . . . . . . . . . . . . . . . . . . . . . 15

6.3.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6.4 Flash memory and programming . . . . . . . . . . 15

6.4.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6.5 DC-to-DC converters . . . . . . . . . . . . . . . . . . . 16

6.6 External memory controller. . . . . . . . . . . . . . . 16

6.6.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6.7 GPIO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6.7.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6.8 Interrupt controller . . . . . . . . . . . . . . . . . . . . . 17

6.8.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6.9 Event router . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.10 General purpose timers . . . . . . . . . . . . . . . . . 18

6.10.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.11 Watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . 18

6.11.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6.12 Real-time clock . . . . . . . . . . . . . . . . . . . . . . . . 19

6.12.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6.13 General purpose DMA controller . . . . . . . . . . 19

6.13.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6.14 UART and IrDA . . . . . . . . . . . . . . . . . . . . . . . . 20

6.14.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6.15 I2C-bus interface . . . . . . . . . . . . . . . . . . . . . . . 20

6.15.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6.16 10-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.16.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.17 Analog I/O. . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.17.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.18 USB 2.0 Hi-Speed device controller . . . . . . . . 21

6.18.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.19 SD/MMC card interface . . . . . . . . . . . . . . . . . 22

6.19.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.20 LCD interface . . . . . . . . . . . . . . . . . . . . . . . . . 23

6.20.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

6.21 Clocking and power control . . . . . . . . . . . . . . 23

6.21.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

6.21.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

6.21.3 Crystal oscillator. . . . . . . . . . . . . . . . . . . . . . . 24

6.21.4 PLLs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

6.21.5 Power control and modes. . . . . . . . . . . . . . . . 24

6.21.6 APBs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6.22 Emulation and debugging. . . . . . . . . . . . . . . . 25

7 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 26

8 Static characteristics . . . . . . . . . . . . . . . . . . . 27

9 Dynamic characteristics. . . . . . . . . . . . . . . . . 31

9.1 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

10 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 39

11 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 40

12 Revision history . . . . . . . . . . . . . . . . . . . . . . . 41

13 Legal information . . . . . . . . . . . . . . . . . . . . . . 42

13.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 42

13.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

13.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 42

13.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 42

14 Contact information . . . . . . . . . . . . . . . . . . . . 42

15 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

LPC2880, 2888 Datasheet by NXP USA Inc.

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