3.3 VOLT CMOS ASYNCHRONOUS FIFO DATASHEET IDT72V01, IDT72V02 IDT72V03, IDT72V04 IDT72V05, IDT72V06
The reads and writes are internally sequential through the use of ring pointers, with no address information required to load and unload data. Data is toggled in and out of the devices through the use of the Write (W) and Read(R) pins. The devices have a maximum data access time as fast as 25 ns.
The devices utilize a 9-bit wide data array to allow for control and parity bit sat the user’s option. This feature is especially useful in data communications applications where it is necessary to use a parity bit for transmission/reception error checking. They also feature a Retransmit (RT) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW to allow for retransmission from the beginning of data. A Half-Full Flag is available in the single device mode and width expansion modes.
These FIFOs are fabricated using high-speed CMOS technology. It has been designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.
IDT72V01 、 IDT72V02 、 IDT72V03 、 IDT72V04 、 IDT72V05 、 IDT72V06 、 IDT72V01L15 、 IDT72V01L25 、 IDT72V01L35 、 IDT72V02L15 、 IDT72V02L25 、 IDT72V02L35 、 IDT72V03L15 、 IDT72V03L25 、 IDT72V03L35 、 IDT72V04L15 、 IDT72V04L25 、 IDT72V04L35 、 IDT72V05L15 、 IDT72V05L25 、 IDT72V05L35 、 IDT72V06L15 、 IDT72V06L25 、 IDT72V06L35 、 72V01L15JG8 、 72V01L35JG8 、 72V0125JGI8 |
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[ applications requiring asynchronous and simultaneous read/writes in multiprocessing ][ rate buffer applications ] |
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Datasheet |
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Please see the document for details |
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Commercial 、 Industrial |
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PLCC |
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English Chinese Chinese and English Japanese |
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11/27/2017 |
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DSC-3033/8 |
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368 KB |
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