Two side-by-side FIFO memory arrays for bidirectional data transfers (IDT72521) 18-bit data buses on Port A side and Port B side Can be configured for or 36-to-36-bit communication Fast 35ns access time Fully programmable standard microprocessor interface Built-in bypass path for direct data transfer between two ports Two fixed flags, Empty and Full, for both the A-to-B and the B-to-A FIFO Two programmable flags, Almost-Empty and Almost-Full for each FIFO Programmable flag offset can be set to any depth in the FIFO Any of the eight flags can be assigned to four external flag pins Flexible reread/rewrite capabilities Six general-purpose programmable I/O pins Standard DMA control pins for data exchange with peripherals 68-pin PGA and PLCC packages

The IDT72511 and IDT72521 are highly integrated first-in, first-out memories that enhance processor-to-processor and processor-to-peripheral communications. IDT BiFIFOs integrate two side-by-side memory arrays for data transfers in two directions. The BiFIFOs have two ports, A and B, that both have standard microprocessor interfaces. All BiFIFO operations are controlled from the 18-bit wide Port A. Port B is also 18 bits wide and can be connected to another processor or a peripheral controller. The BiFIFOs have a 9-bit bypass path that allows the device connected to Port A to pass messages directly to the Port B device. Ten registers are accessible through Port A, a Command Register, a Status Register, and eight Configuration Registers. The IDT BiFIFO has programmable flags. Each FIFO memory array has four internal flags, Empty, Almost-Empty, Almost-Full and Full, for a total of eight internal flags. The Almost-Empty and Almost-Full flag offsets can be set to any depth through the Configuration Registers. These eight internal flags can be assigned to any of four external flag pins (FLGA-FLGD) through one Configuration Register. Port B has programmable I/O, reread/rewrite and DMA functions. Six programmable I/O pins are manipulated through

two Configuration Registers. The Reread and Rewrite controls will read or write Port B data blocks multiple times. The BiFIFO has three pins, REQ, ACK and CLK, to control DMA transfers from Port B devices.

Symbol DA0-DA17 Name Data A Chip Select A Data Strobe A Read/Write A I/O I Description Data inputs and outputs for the 18-bit Port A bus. Port A is accessed when Chip Select A is LOW. Data is written into Port A on the rising edge of Data Strobe when Chip Select is LOW. Data is read out of Port A on the falling edge of Data Strobe when Chip Select is LOW. This pin controls the read or write direction of Port A. When CSA is LOW and R/WA is HIGH, data is read from Port A on the falling edge of DSA. When CSA is LOW and R/WA is LOW, data is written into Port A on the rising edge of DSA. When Chip Select A is asserted, 0, A1, and Read/Write A are used to select one of six internal resources. Data inputs and outputs for the 18-bit Port B bus.

O If Port B is programmed to processor mode, this pin functions as an input. If Port B is programmed to peripheral mode this pin functions as an output. This pin can function as part of an Intel-style interface (RB) or as part of a Motorola-style interface (DSB). As an Intel-style interface, data is read from Port on a falling edge of RB. As a Motorola-style interface, data is read on the falling edge of DSB or written on the rising edge of DSB through Port B. The default is Intel-style processor mode. (RB as an input). O If Port B is programmed to processor mode, this pin functions as an input. If Port B is programmed to peripheral mode this pin functions as an output. This pin can function as part of an Intel-style interface ( WB) or as part of a Motorola-style interface (R/ WB). As an Intel-style interface, data is written to Port on a rising edge of WB. As a Motorola-style interface, data is read (R/WB = HIGH) or written (R/WB = LOW) to Port B in conjunction with a Data Strobe B falling or rising edge. The default is Intel-style processor mode as an input.) Loads A B FIFO Read Pointer with the value of the Reread Pointer when LOW. Loads B A FIFO Write Pointer with the value of the Rewrite Pointer when LOW. Loads the Reread Pointer with the value of the AB FIFO Read Pointer when HIGH. Loads the Rewrite Pointer with the value of the BA FIFO Write Pointer when HIGH. When Port B is programmed in peripheral mode, asserting this pin begins a data transfer. Request can be programmed either active HIGH or active LOW. When Port B is programmed in peripheral mode, Acknowledge is asserted in response to a Request signal. This confirms that a data transfer may begin. Acknowledge can be programmed either active HIGH or active LOW. This pin is used to generate timing for ACK, peripheral mode.

These four outputs pins can be assigned any one of the eight internal flags in the BiFIFO. Each of the two internal FIFOs (AB and BA) has four internal flags: Empty, Almost-Empty, Almost-Full and Full. Six general purpose I/O pins. The input or output direction of each pin can be set independently.

A LOW on this pin will perform a reset of all BiFIFO functions. There are two +5V power pins. There are five Ground pins at 0V.