IDT72274 datasheet - Variable Width Supersynco Fifo 8,192 X 18 or 16,384

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Details, datasheet, quote on part number: IDT72274

Part	IDT72274
Category	Logic => FIFOs
Description	Variable Width Supersynco Fifo 8,192 X 18 or 16,384 X 9 16,384 X 18 or 32,768 X 9
Company	Integrated Device Technology, Inc.
Datasheet	Download IDT72274 Datasheet
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Features, Applications

Select 16384x 9 organization (IDT72264) Select x 9 organization (IDT72274) Flexible control of read and write clock frequencies Reduced dynamic power dissipation Auto power down minimizes power consumption 15 ns read/write cycle time (10 ns access time) Retransmit Capability Master Reset clears entire FIFO, Partial Reset clears data, but retains programmable settings Empty, full and half-full flags signal FIFO status Programmable almost empty and almost full flags, each flag can default to one of two preselected offsets Program partial flags by either serial or parallel means Select IDT Standard timing (using EF and FF flags) or First Word Fall Through timing (using OR and IR flags) Easily expandable in depth and width Independent read and write clocks (permits simultaneous reading and writing with one clock signal) Available in the 64-pin Thin Quad Flat Pack (TQFP), 64pin Slim Thin Quad Flat Pack (STQFP) and the 68-pin Pin Grid Array (PGA) Output enable puts data outputs into high impedance High-performance submicron CMOS technology

Industrial temperature range +85OC) is available, tested to military electrical specifications

The IDT72264/72274 are monolithic, CMOS, high capacity, high speed, low power first-in, first-out (FIFO) memories with clocked read and write controls. These FIFOs have three main features that distinguish them among SuperSync FIFOs: First, the data path width can be changed from as a result, halving the depth. A pin called Memory Array Select (MAC) chooses between the two options. This feature helps reduce the need for redesigns or multiple versions of PC cards, since a single layout can be used for both data bus widths. Second, IDT72264/72274 offer the greatest flexibility for setting and varying the read and write clock (WCLK and RCLK) frequencies. For example, given that the two clock frequencies are unequal, the slower clock may exceed the faster by, at most, twice its frequency. This feature is especially useful for communications and network applications where clock frequencies are switched to permit different data rates.

MAC MEMORY ARRAY CONFIGURATION OUTPUT REGISTER READ CONTROL LOGIC

SyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.

For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.

Finally,of all SuperSync FIFOs, the IDT72264/72274 offer the lowest dynamic power dissipation. These devices meet a wide variety of data buffering needs. In addition to those already mentioned, applications include such as optical disk controllers, Local Area Networks (LANs), and inter-processor communication. Both FIFOs have an 18-bit input port (Dn) and an 18-bit output port (Qn). The input port is controlled by a free-running clock (WCLK) and a data input enable pin (WEN). Data is written into the synchronous FIFO on every clock when WEN is asserted. The output port is controlled by another clock pin (RCLK) and enable pin (REN). The read clock can be tied to the write clock for single clock operation or the two clocks can run asynchronously for dual clock operation. An output enable pin (OE) is provided on the read port for three-state control of the outputs. The IDT72264/72274 have two modes of operation: In the IDT Standard Mode, the first word written to the FIFO is deposited into the memory array. A read operation is required to access that word. In the First Word Fall Through Mode (FWFT), the first word written to an empty FIFO appears automatically on the outputs, no read operation required. The

state of the FWFT/SI pin during Master Reset determines the mode in use. The IDT72264/72274 have five flag functions, EF/OR (Empty Flag or Output Ready), FF/IR (Full Flag or Input Ready), and HF (Half-full Flag). The EF and FF functions are selected in the IDT Standard Mode. The IR and OR functions are selected in the First Word Fall Through Mode. IR indicates that the FIFO has free space to receive data. OR indicates that data contained in the FIFO is available for reading. is a flag whose threshold is fixed at the half-way point in memory. This flag can always be used irrespective of mode. PAE and PAF can be programmed independantly to any point in memory. They, also, can be used irrespective of mode. Programmable offsets determine the flag threshold and can be loaded by two methods: parallel or serial. Two default offset settings are also provided, such that PAE can be set or 1023 locations from the empty boundary and the PAF threshold can be set or 1023 locations from the full boundary. All these choices are made with LD during Master Reset.

TQFP (PN64-1, order code: PF) STQFP (PP64-1, order code: TF) TOP VIEW

NOTES: 1. When the data path is selected be 9 bits wide (MAC is HIGH), - D17 may either be tied to ground or left open, - Q17 must be left open.

In the serial method, SEN together with LD are used to load the offset registers via the Serial Input (SI). In the parallel method, WEN together with LD can be used to load the offset registers via Dn. REN together with LD can be used to read the offsets in parallel from Qn regardless of whether serial or parallel offset loading is selected. During Master Reset (MRS), the read and write pointers are set to the first location of the FIFO. The FWFT line selects IDT Standard Mode or FWFT Mode. The LD pin selects one of two partial flag default settings or 1023) and, also, serial or parallel programming. The flags are updated accordingly. The Partial Reset (PRS) also sets the read and write pointers to the first location of the memory. However, the mode setting, programming method, and partial flag offsets are not altered. The flags are updated accordingly. PRS is useful for resetting a device in mid-operation, when reprogramming offset registers may not be convenient. The Retransmit function allows the read pointer to be reset to the first location in the RAM array. It is synchronized to

RCLK when RT is LOW. This feature is convenient for sending the same data more than once. If, at any time, the FIFO is not actively performing a function, the chip will automatically power down. This occurs if neither a read nor a write occurs within 10 cycles of the faster clock, RCLK or WCLK. During the Power Down state, supply current consumption at a minimum. Initiating any operation (by activating control inputs) will immediately take the device out of the Power Down state. The IDT72264/72274 are depth expandable. The addition of external components is unnecessary. The IR and OR functions, together with REN and WEN, are used to extend the total FIFO memory capacity. The FS line ensures optimal data flow through the FIFO. It is tied to GND if the RCLK frequency is higher than the WCLK frequency or to Vcc if the RCLK frequency is lower than the WCLK frequency The IDT72264/72274 is fabricated using IDT's high speed submicron CMOS technology.

NOTES: 1. When the data path is selected be 9 bits wide (MAC is HIGH), - D17 may be tied to ground or left open, - Q17 must be left open. 2. DNC = Do not connect

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