35ns parallel port access time, 45ns cycle time 50MHz serial input/output frequency Serial-to-parallel, parallel-to-serial, serial-to-serial, and parallel-to-parallel operations Expandable in both depth and width with no external components FlexishiftTM Sets programmable serial word width from 4 bits to any width with no external components Multiple flags: Full, Almost-Full (Full-1/8),Full-MinusOne, Empty, Almost-Empty (Empty + 1/8), Empty-PlusOne, and Half-Full Asynchronous and simultaneous read or write operations Dual-Port, zero fall-through time architecture Retransmit capability in single-device mode Packaged in 44-pin PLCC Industrial temperature range to +85oC)

High-speed data acquisition systems Local area network (LAN) buffer High-speed modem data buffer Remote telemetry data buffer FAX raster video data buffer Laser printer engine data buffer High-speed parallel bus-to-bus communications Magnetic media controllers Serial link buffer

The IDT72103/72104 are high-speed Parallel-Serial FlFOs to be used with high-performance systems for functions such as serial communications, laser printer engine control and local area networks.

SERIAL INPUT SI SIX SICP /PI /PO DATA INPUTS 8 ) SERIAL INPUT CIRCUITRY FLAG LOGIC SERIAL/ PARALLEL CONTROL RAM ARRAY x 9

�1999 Integrated Device Technology, Inc. For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.

A serial input, a serial output and two 9-bit parallel ports make four modes of data transfer possible: serial-to-parallel, parallel-to-serial, serial-to-serial, and parallel-to-parallel. These devices are expandable in both depth and width for all of these operational configurations. These FIFOs may be configured to handle serial word widths of four or greater using IDT's unique Flexishift feature. Flexishift allows serial width and depth expansion without external components. For example, you may configure x 24 FIFO using three in a serial width expansion configuration.

Seven flags are provided to signal memory status of the FIFO. The flags are FF (Full), AF (7/8 full), FF�1 (Full-minusone), EF (Empty), AE (1/8 full), EF+1 (Empty-plus-one), and HF (Half-full). Read (R) and Write (W) control pins are provided for asynchronous and simultaneous operations. An Output Enable (OE) control pin is available on the parallel output port for high-impedance control. The depth expansion control pins XO and Xl are provided to allow cascading for deeper FlFOs. The IDT72103/72104 are manufactured using IDT's CMOS technology.

Symbol Name D0-D8 Data Inputs Serial Input Word Width Select RS Reset I/O Description I/O In a parallel input configuration � data inputs for 9-bit wide data. In a serial input configuration � one of the nine output pins is used to select the serial input word width. I When RS is set low, internal READ and WRITE pointers are set to the first location of the RAM array. EF, EF+1, AEF are all LOW after a reset, while FF, FF-1, HF are HIGH after a reset. W Write I A parallel word write cycle is initiated on the falling edge W if the FF is high. When the FIFO is full, FF will go low inhibiting further write operations to prevent data overflow. In a serial input configuration, data bits are clocked into the input shift register and the write pointer does not advance until a full parallel word is assembled. One of the pins, Di, is connected to W and advances the write pointer every i-th serial input clock. R Read I A read cycle is initiated on the falling edge R if the EF is HIGH. After all the data from the FIFO has been read EF will go LOW inhibiting further read operations. In a serial output configuration, a data word is read from memory into the output shift register. One of the pins, Qj, is connected to R and advances the read pointer every j-th serial output clock. FL/RT First Load/ I This is a dual-purpose pin. In multiple-device mode, FL/RT is grounded to indicate the first Retransmit device loaded. In single-device mode, FL/RT acts as the retransmit input. Single-device mode is initiated by grounding the XI pin. Xl Expansion I In single-device mode, XI is grounded. In depth expansion or daisy chain mode, XI is connected to the XO pin of the previous device. OE Output Enable I When OE is LOW, both parallel and serial outputs are enabled. When OE is HIGH, the parallel output buffers are placed in a high-impedance state. Q0-Q8 Data Outputs/Serial In a parallel output configuration - data outputs for 9-bit wide data. In a serial output Output Word Width Select configuration - one of nine output pins used to select the serial output word width. FF Full Flag FF is asserted LOW when the FIFO is full and further write operations are inhibited. When the FF is HIGH, the FIFO is not full and data can be written into the FIFO. FF-1 Full-1 Flag O FF-1 goes LOW when the FIFO memory array is one word away from being full. It will remain LOW when every memory location is filled. XO/HF Expansion Out/ HF is LOW when the FIFO is more than half-full in the single device or width expansion modes. Half-Full Flag The HF will remain LOW until the difference between the write and read pointers is less than or equal to one-half of the FIFO memory. In depth expansion mode, a pulse is written from XI of the next device when the last location in the FIFO is filled. Another pulse is sent from Xl of the next device when the last FIFO location is read. AEF Almost-Empty/ O When AEF is LOW, the FIFO is empty to 1/8 full or 7/8 full to completely full. If AEF is HIGH, Almost-Full Flag then the FIFO is greater than 1/8 full, but less than 7/8 full. EF+1 Empty+1 Flag O EF+ 1 is LOW when there is zero or one word in the FIFO memory array. EF Empty Flag O EF goes LOW when the FIFO is empty and further read operations are inhibited. FF is HIGH when the FIFO is not empty and data reads are permitted. Sl Serial Input Expansion I Data input for serial data. SO Serial Output Expansion O Data output for serial data. SICP Serial Input Clock I This pin is the serial input clock. On the rising edge of the SICP signal, new serial data bits are read into the serial input shift register. SOCP Serial Output I This pin is the serial output clock. On the rising edge of the SOCP signal, new serial data bits Clock are read from the serial output shift register. SIX Serial Input I SIX controls the serial input expansion for word widths greater than 9 bits. In a serial input Expansion configuration, the SIX pin of the least significant device is tied HIGH. The SIX pin of all other devices is connected to the D8 pin of the previous device. In parallel input configurations or serial input configurations of 9 bits or less, SIX is tied HIGH. SOX Serial Output I SOX controls the serial output expansion for word widths greater than 9 bits. In a serial output Expansion configuration, the SOX pin of the least significant device is tied HIGH. The SOX pin of all other devices is connected to the Q8 pin of the previous device. In parallel output configurations or serial output configurations of 9 bits or less, SOX is tied HIGH. SI/PI Serial/Parallel Input I When this pin is HIGH, the FIFO in a parallel input configuration and accepts input data through D0-D8. When SI/PI is LOW, the FIFO in a serial input configuration and data is input through Sl. SO/PO Serial/Parallel Output I When this pin is HIGH, the FIFO in a parallel output configuration and sends output data through Q0-Q8. When SO /PO is LOW the FIFO in a serial output configuration and data is input through SO. GND Ground Five ground pins for the PLCC. VCC Power One + 5V power pin.