Next-generation hand-held products: - Communicators - Smartphones - Subnotebook computers Digital consumer appliances featuring: - 3D graphics - Web content - Voice recognition and synthesis - Digital video - High-speed connectivity

The ARM10TM Thumb� Family of processors will deliver 400 Dhrystone 2.1 MIPS at 300MHz, and 600 MFLOPS for 3D graphics and floating point DSP. Process portable to high performance 0.25 micron and 0.18 micron CMOS fabrication processes, the ARM10 processor units will be licensed to multiple semiconductor partners, offering OEMs guaranteed continuity of supply. The ARM10 Thumb Family maintains traditional ARM values of low system cost, low power consumption, and use within larger system-on-chip designs. The Thumb 16-bit compressed instruction set gives a reduction in the required memory size and bandwidth, which directly reduces system cost.The ARM10TDMITM integer unit features the ARM 32-bit RISC instruction set, and Thumb compressed 16-bit instruction set. The ARM10TDMI unit employs parallel instruction execution, branch prediction, and a non-blocking data cache interface to achieve high performance on real applications.The ARM1020TTM cached processor macrocell is built around the ARM10TDMI unit, and also features large on-chip instruction and data caches, an MMU with demand paged virtual memory support, a write buffer, and a new high-bandwidth AMBATM Advanced High-Speed Bus (AHB) system-on-a-chip bus interface. The ARM10200 Reference Device is a packaged chip containing an ARM1020T core with the VFP10TM coprocessor, a high performance SDRAM memory interface and an on-chip Phase Locked Loop (PLL). The ARM10200 can be used for all types of evaluation, especially benchmarking and system prototyping.

Multi-sourced high-performance, low-power processor macrocells High-performance vector floating point delivers 3D graphics and floating point DSP Access to existing ARM architecture, tools, OS, and code-base Low system cost via excellent code density High performance allows cost saving via migration of hardware features to software implementations System-on-a-chip ready allowing rapid integration with short time to market Designed to run sophisticated OS such as Linux, EPOC, and WindowsCE

The ARM10 processors feature EmbeddedICETM JTAG software debug, and the AMBA AHB multi-master on-chip bus architecture that provides for peripheral design reuse and efficient production test. ARM and its partners provide ASIC simulation models, and co-simulation tools to enable the design process.

The ARM10 Thumb Processor Family is backwards compatible with the ARM7 Thumb Family, the ARM9 Thumb Family, and StrongARM processor families, giving designers software-compatible processors with a range of price/performance points from 60 MIPS to 400 MIPS. Support for the ARM architecture today includes the WindowsCE, EPOC, JavaOS, and Linux operating systems, more than 25 Real Time Operating Systems, Co-simulation tools from leading EDA vendors, and a variety of software development tools. � Copyright ARM Limited. All rights reserved.

The ARM1020T includes cache and memory management functions to support a full demand-paged virtual memory operating system and support for real-time embedded operating systems.

Twin 64-entry Translation Lookaside Buffers (TLBs) provide fast access to the most recent address translations. ARM1020T also provides TLB lock-down. This allows critical translations to remain in the TLB to ensure predictable access to realtime code.

Two 32KB caches are implemented, one for instructions, the other for data, both with an eight-word line size. These caches connect to the integer unit via 64-bit buses, to allow two instructions to be passed into the instruction prefetch unit every cycle, and to allow load and store multiple instructions to transfer two 32-bit registers every cycle.

Cache lock-down is provided to allow critical code sequences to be locked into the cache to ensure predictability for real-time code. The cache replacement policy can be selected by the operating system as either fully random or round-robin. Both caches are 64-way set-associative.

The data cache supports nonblocking hit-under-miss operation. Nonblocking operation allows instructions that occur after a data cache miss to

continue execution before the data is returned. The hit-under-miss operation allows subsequent load or store instructions after a cache miss to access the data cache. Together these mechanisms can provide significantly higher performance for applications that incur high data cache miss rates.

ARM1020T also incorporates a double word 8-entry write buffer, to avoid stalling the processor when writes to external memory are performed.

The ARM10TDMI integer unit is an implementation of the ARM Architecture Version 5T, the latest implementation of the ARM Architecture. is a superset of the ARMv4 ISA implemented by the StrongARM processors and the ARMv4T ISA implemented by the ARM7 Thumb and ARM9 Thumb Family processors.

All exceptions have banked registers for R14 and R13. After an exception R14 holds the return address for exception processing. This address is used both to return after the exception is processed and to address the instruction that caused the exception. R13 is banked across exception modes to provide each exception handler with a private stack pointer. The fast interrupt mode also banks registers 12 so that interrupt processing can begin without the need to save or restore these registers. A seventh processing mode, System mode, does not have any banked registers. It uses the User mode registers. System mode runs tasks that require a privileged processor mode and allows them to invoke all classes of exceptions.

normal interrupt (IRQ) memory aborts (used to implement memory protection or virtual memory) attempted execution of an undefined instruction software interrupts (SWIs).

All ARM instructions (with the exception of BLX) are conditionally executed. Instructions optionally update the four condition code flags (Negative, Zero, Carry and Overflow) according to their result. Subsequent instructions are conditionally executed according to the status of flags. Fifteen conditions are implemented.

ARM10TDMI executes two instruction sets, the 32-bit ARM instruction set, and the 16-bit Thumb instruction set. The ARM instruction set allows a program to achieve maximum performance with the minimum number of instructions. The simpler Thumb instruction set offers much increased code density for code that does not require maximum performance. Code can switch between the ARM and Thumb instruction sets on any procedure call.

The ARM and Thumb instruction sets can be divided into four broad classes of instruction data processing instructions load, store and swap instructions branch instructions coprocessor instructions.

All other processor states are held in status registers. The current operating processor status is in the Current Program Status Register (CPSR). The CPSR holds 4 ALU flags (Negative, Zero, Carry and Overflow), two interrupt disable bits (one for each type of interrupt), a bit to indicate ARM or Thumb execution, and 5 bits to encode the current processor mode. All 5 exception modes also have a Saved Program Status Register (SPSR) which holds the CPSR of the task immediately before the exception occurred.

The Integer Unit consists a 32-bit datapath and associated control logic. The datapath contains 31 general-purpose registers, coupled to a full shifter, Arithmetic Logic Unit, and multiplier. At any one time 16 registers are visible to the user. The remainder are banked registers used to speed up exception processing. Register 15 is the Program Counter (PC) and can be used in memory access instructions to reference data relative to the current instruction address. R14 holds the return address after a subroutine call. R13 is used (by software convention) as a stack pointer.

The data processing instructions operate on data held in general purpose registers. Of the two source operands, one is always a register. The other has two basic forms, an immediate value or a register value optionally shifted. If the operand is a shifted register the shift amount may have an immediate value or the value of another register. Four types of shift can be specified. Most data processing instructions can perform a shift followed by a logical or arithmetic operation. Multiply instructions come in two classes, (normal) 32-bit result and (long) 64-bit result variants. Both

ARM10TDMI supports 5 types of exception, and a privileged processing mode for each type. The 5 types of exceptions are: fast interrupt (FIQ)