ADG3308: Input Driving and Output Load Requirements

FAQ: What are the input driving and output load requirements of the ADG3308?

Answer:

To ensure the correct operation of the ADG3308, the circuit that drives the input of the device should be able to ensure the rise/fall times of less than 3-ns when driving a load consisting of a 6-kΩ resistor in parallel with the input capacitance of the ADG3308 channels.

The ADG3308 level translator is designed to drive CMOS-compatible loads. If a high current driving capability is needed, it is recommended to use external buffers such as ADA4891, AD8061, and AD8063 between the ADG3308 outputs and loads.