Settings
Fast Delivery
Payment Types
Marketplace Product
Z8420, Z84C20 Specification Datasheet by Zilog
Product Specification
. i r
23420/234020 NMOS/CMOS
280 ° PIO
Parallel Input/Output
FEATURES
I Frames 3 drreol menace between 280 mrcrocompuler
systems and penpheral devices.
I Two pans wrlh rnlerrum-dnven handshake lor lssl
response.
I Four programmable operaung modes Oulpul, Input,
Brdrrecucnal (Pen A only), and Ba Convol
I Programmable rmermprs on
condmons. (1.5 mV @ I,5V)
I NMOS versinn tor oosl sensiuve performance salmon
I CMOSversbnlogmedss‘ms requinng high speed and
low power consumption
peripheral sratus
l NMOSW-‘MHLZm-GJTMHZ.
l CMOS 28402006 - DC to 6 l7 MHZ.
ZSJCZOOB - DC l0 8 MHZ
I Smndard ZBO Famlly busraquest and priolmzed
rmerrupl-requesl daisy charns Implemented wrlhoul
externallogic.
I The am Fan B ompuls can drive Damnglon Iranslslors
(15 mA at 1.5V)
I sMszersror-suppm amunchuamm
non.
GENERAL DESCRIPTION
T‘IeZm PIO anueruocmm (hereinauermiemdloas
me ZsoPIOorPIonsapmgmmaue, warm device
MWaTrL—cmwbleinlenaoebeiween periph-
arddevloesaMlleBOCPU (mendalNo‘elfle
QFPpmgeisomyavdlaMehCMOSvemtheCFU
mfiguraslhemPIOIoinadaoewflhawidemngeM
-. a.
Dr n.
u. ~.
I": o. u,
u. ,I N
o. n. m .
r. u.
1:, Ir
m n, your .
m n.
m
"m ___.
w rfi
run-nun
wlvml. — ‘5‘
_ .m
Flynn I. Pln Functlom
peripheral devices lha| are comparable with the 280 FIG
include "1051 keybcards, paper tape readers and punches,
primers. and PROM programmers.
one characlerisuc 0! me 280 penphelal controllers that
separates met" irom other inleflaoe controllers I9 that all
HE' V -:r».
.c. -Jn.
n.|:- -:I-.
2!: . .13.:
m: . .nm
.1: . x3»
“,1: r «In.
«4:. n3».
mg. .13».
.::E: "W 213:
m: r: ”J"-
...c u .3...
an: u "an.
M: u .3...
m: u 1.3m
m: ., Mara
AIME .- ngm
I: r. njrso
mg. 2.3..“
mm- 2m min Dull—ln-UM mm. (DIP).
Prumlgrrmenu
67
PS018001-0602
LQFP package is only available in CMOS version.
The CPU Configures the Z80 PIO to interface with
a wide range of
MPOv-vvvvvééb
uncantuuuttn
III :05
u, am
a. xrn.
m an.
m )5».
It: un.
can tan.
m urn.
u. urn
at. am
N am
urintrnnuunnn
46$; «pgatatwé o
Flgun 2p. «port Otllp cantor.
Mn mama
lilllsfliié
O
325:: new;
Flaure 2c. u-pln Quad Flu Puck Ptn
Assignments.
mum
on: m
m—v i "T-
— m
:9
Home 3. P30 In I W 1.0 Funny Emlromml
data transter between the peripheral device and the CPU tS
accompllstted under mtermpt contra. Thus, the interrupt
IOQIC at the PIO permtts tuII use 01 the etficient rnterrupt
capabilttres or the 250 CPU durlng no transters, All togtc
necessary to implement a tully nested Interrupt structure ts
tnctuded in the PIO (thure 3).
Another feature otttte PIO Is the abl‘ity to Interrupt the CPU
upon occurrence ot specttted status CondlllOnS tn the
pertpheral device For example. the PIO can be
programmed to rnterrupt it any specnied pertptrerat etarrn
condmons should occur. Thts Interrupt Capabtttly reduces
the tune the processor must spend In potling peflphenal
status.
The 280 FIG intertaoes to peripherats VIE two Independent
general-purpose :10 ports, designated Port A and Part B.
Each pet! has ergttt data bits and two handshake stgnalst
Ready and Strobe. whrctt control data Iranster. The RWY
output tndtcatesmtl’te peripheral that the port ts remy tor a
data transter. Strobe is an input rrom the perIpheral that
indicates when a data transter has occurred.
Operatlllg Model The 250 FIG ports can be programmed
to operate in tour modes: Output (Mode 0). tnput (Mode 1).
Bidtrectional (Mode 2t and BIt Controt (Mode 3)
Elmer Pon A or PM E can be programmed to output data In
Mode 0 Both ports have output regtsters that are
indtvtdually addressed by the CPU. data can be wmten to
ettrter port at any time When data Is wrttten to a port. an
acttve Ready output tndtcates to the external Get/Ice that
data Is available at the assocrated port and IS ready [or
transter to the enemy device Alter the data "angler, the
external device responds with an active Strobe Input thtch
generates an Interrupt, .1 enabled
Ettter Port A or Port 5 can be programmed to mgflm rn
Mode 1, sea. port has an tnput regtstet padres try the
68
PS018001-0602
LQFP Pin Assignments
CPU. When the CPU reeds date lrcrn a port, the PIO sets the
needy s‘gnal. which is deteded by the external device. The
emermldevioemenptaoesdatnonmewllmandstmbes
the V0 port. which latches the data Into the Port Input
Register, resets Heady, and triggers the Interrupt Request, It
enabled. The CPU can read the Input data at any time,
whiter again eats Heady.
Mode 2 is blditectiortal and uses only Port A, plus the
Interrupts and handshake Signals lrum both ports. Port B
must be set to Mode 3 and masked ott lrom generating
Interrupts. In operation. Port A as used tor both data Input
and output. Output operation ls stmllal to Mode 0 went
that date is allowed autumn the PortA bus only when m
is Um For Input. operation ls similar to Mode 1. wept that
the data input uses the Part B handshake signals and the
Pen 5 interrupt, it enabled.
BottiportscanbeussdlnMode3.lnmismode.the
indvtduat bitsale defined aseithel thputot outptn bits This
ptwtdes up to eight separate, indivtdually delined bits tot
each port During operation. Ready and Strobe are not
used tns16ad. an imettupt is generated "the oorditlon ot
one input changes. or tall inputs change The requirements
tar generaung an Interrupt are detined during the
programming operation; the active level is specified as
either ngh or Low. and the logic condition is specified as
either one input active (on) or all inputs active (AND). For
example. ltthe poms mogtammed tolactrve Lowlnpuls and
the logic lunction is AND. then all Inputs at the specified pon
must go Lowto generate an Interrupt
Data outputs ate controlled by the CPU and can be written
or changed at any time.
I lndlvtdual bl|scan be masked ott.
I The handSIake signals are not used in Mode 3, Ready IS
hetd UM, and Strobe is disabled
I When using the 230 Fla interrupts. the 200 CPU
interruptrnodeinustbesettoModez
INTERNAL STRUCTURE
The Internal stmcture ol the 230 FIG consists or a 250 CPU
bus inlerlace. internal control logic. Port A lIO logic. Port 3
IIOtogic. and intenupt control |ogio(thure 4). TheOPU bus
inlenace logic alkms the 230 FIG to Intenace directly to the
250 CPU with no other external logic. The internal control
logic synchronizes the CPU data bus to the peripheral
device Inteneces (Port A and Perl a), The two llo ports (A
and B) are virtually identical and are used to interlace
directly to peripheral devices
Port Loglct Each part contains separate input and output
registers. handshake controt logic. and the control registers
shown in Figure 5. All datattanstels between me petlptletal
unit and the CPU ueethe data input and output registers,
The handshake logic assoc-titted with 93m port controls the
data transters through the input and the output registers,
The mode control register (two bits) selects one at the tour
The Bit Oomrol rnode (Mode 3) uses the remaining registers
The input/output control register specifies which ot the eight
data bits in the port ateto beompvm and enablesthese bits:
the remaining bits are Inputs. The mask register and the
mask control register govern Mode 3 interrupt conditions
The mask register epecilies which ot the bite in the pen are
active and which are masked or lnaDXlVE.
The mask control register specflla two conditions lltst.
whether the saliva state of the Input btts is High at Low, and
second. whether an interrupt Is genemled when any one
unmasked input bit is active (OR condition) or it the Interrupt
is generated when all unmasted input bits are actrue (AND
condition),
Intermm WI Layla. melmettuptconttot logic section
handles all CPU Interrupt protocol tor nestedrpnortty
Itttettupl sttuctutes Arty device's Dill/steal location In a
programmable operating modes
Intent”; 3
com run
some my Q“ mourn-oi
A it «—
l0 Mama
I —‘
‘+’ cw m...
mu m remit-is :rHHcE‘
—‘/-> W e
whom «to W“
I on mm
.c }....iea.i.tr
lirrumr '—>
cerium
i
Imam" comm um
Figure 4. Dock Dinar-m
PS018001-0602
daisy-chain contigurahon determines its pnonty Two lines
(IEI and IEO) are plowded in each PIO to term this oaisy
Chain. Thedeirice closesttothe CPU has the highest pllunty.
Wllhln a FIG Pod A Interrupts have htgheT pflomy than
these olPort a. lntheoyieinput. byte output or bldttecltonal
modes. an interrupt can be generated whenever the
peripheral requests a new by|etvans19n In the on control
mode, an inieiiuot Can be genetaled when the peripheral
status matches a programmed value. The Plo pieyictee tor
complete control oi nested Interrupts That is lower priority
devices may not inteirupt higher priority devlces that have
not had Ihetl Interrupt sen/toe voutlnes Compteled by the
CPU Higher priority devtces may interrupt the Selvlclng at
tower priority devices
It the CPU an interrupt Mode 2) accepts an interrupt, the
interrupting deirice must oioyioe an obit interrupt vector tor
the CPU Thts vector Ioimse pointer to a location in memory
where the eddressot the interrupt eerVice routine is located.
The 6-bn vector liom the interrupting devtoe Iorms the least
stgnlficant eight hits at the indirect pointer while the I
Register in the CPU moi/ides the most eigmlicant eight hits
ot the pointer Each port (A and a) has an independent
interrupt vector The least signiticant on oi the vector is
automatically set to 0 within the PIO because the pointer
must point to two adjacent! memory locations toia comptete
|6~Dl| address,
Unllke the other 230 peripherals the PIO does not eneote
interrupts Immediately otter pvoglammtng tt waits until W
goes Low (e g , dunng an opcode tetch) This condition is
unlmponanl in the zoo envuonrnem but might not he it
another lype oi CPU is used
The Plo decodes the RETI "Return From Interrupt)
instruction directly [tom the CPU deta bus so that etch PIO
in the system know: at at times whether it is being servtced
try the CPU interrupt service routine No other
communication wrth the CPU is required
cpu one we Logic. TheCPU bus intertece logic iiiteitaoes
the 280 FIG divaclly In the 280 CPU, so no external toglc Is
mastery For large systems, however address dacoaers
and/or outlets maybe necessary
Internet Control Logic. This logic receives the control
- words tor each con during programming and, In turn,
controls the operating lunctione olthe zoo PIO The control
logic synchronizes the port operations, contiots the port
mode. port addressing selects the leadlwme Dunalunt and
issues appmpnate Commandsto the ports anct the interrupt
logic The 290 PIO doesnot Become—write Inpu| trom the
CPU. instead, the FE. 05‘ (2/0 and IORO stgnals internalty
generate the WNE input.
L MW" '
mum
“Lang.
non: mm
mm .um
mitten
all” WWW
it...“
mu
we...“ gm;
mm
F>emmm
w W em
mm m. em
mine. _> ~50...“ C new
we turn
my
WEIRD" HAND _’
a...“ meet.“
my mum n—me mm
W ._
'Iludwtlmnnn-ufimlywflwmmflmlnlmnmmtmpfinwkn
wnmm
Flgwe 5. Typical port l/o Block Dllgnm
70
PS018001-0602
PROGRAMMING
Mods 0, 1. or 2. (lnpul. Oulpul, or Bidtvecn’onal).
Pragrarnrmng a port tot Mode 0. 1 , or 2 requlres at least one.
and up Io three controt words per port These Wolds are
Mode Control Word (Figure 6). Selects the pen operating
mode Tms word is quuth and may be wntten at anytime
Interrupt VeclorWomd(Figure 7), The 230 FIG IS destgned
to. use win the 230 CFU In Inlenupl Mode 2 Thvs wotd
must be programmed tl mtermpts arete be used.
Inmrupt Control Word (Figure 9) or lump! Dlsable
Wont {figure It) Controls the enable or drsable ot the PIO
interrupt tunctton
Mod. a net Controt) ProgrammtrIg a port tor Mode 3
quulresa| “2351 two. and upto tour. control words
Moan ContnI Wold (Figure 6) Selects the pen opevating
mode Thus word IS required and may be wmten at any fine.
I/o Reglmr Comm! Wont (Figure B). When Mode 3 IS
selected, me Mode Controt Word must be renewed by the
no Control Word, The wotd oonngures the IIO eontrot
regtster, which defines which pontnes are inputs omnputs,
ThIs word Is requtred
_|: Ingram-mi
communal?
mm:
rm: e
um t
was a
m: s
Flynn a, node cannot Wont
¥L .mnnnmum
vuvou
use» sumtso INVEIIIAIPV
mm
FIgure 7. Interrupt V09“)! Word
EEEEREEE
T o 5515 mm cum"
t em m ro mm
figure It IIO met-m Comm! Wald
Interrupt VectorWomthure 7t The 260 PIO is destgned
tor use mm the 230 CPU In Inlerlupl Mode 2. The word
must beprogvammed it Interrupts areto beused
InIerrupI Comml Word. In Mode 3. handshake ts not
used. Interrupts are generated as a Iogtc tunctton ol the
Input signal revels. The Inler'UDl cannot wore sets the logtc
commons and the Iogrc Ievets requned tor genemmg an
Interrupt Two Iogrc oondmons or Iunchons are aranabte
AND (rt all Input btts change to the amrvelevelt an Interrupt Is
triggeted). and 0H ("anyone ollhempul buschangestothe
active IeveI, an Interrupt ts tnggered) Ian [)5 sets the rogue
Iunctton, as shown tn FIguIe 9 The acltve level at the Input
bus can be set ether Htgh or Low. The active tevel ts
oomroled by Bn D5
Mask Comml Word. This wold sets the mask control
regiaet. aflomng any unused btlslobemesked on It any bots
aretobemssked,thenmrnustbeset WhenDtisseuhe
next word wrmen lo Ihe pod mus( be a mask control MTG
(FIguIe to;
‘lmmlpl Dluble Wad. Thls cannot wold can be used to
enable or dtsable a port tnterrupt. It can be used wtthout
changtng the rest 0! the intenuptcuntrot word (FIgure t t).
_l: mmmmnmm
t. uAurotqustt)
“WW
I .mmm
”armrmrmmm
more
I Manama-um" mum-
r-r-mm DIM
) mm'lwmn-mwmt mu
Wmuwnmm It
Flgurl 9. Immtpt Comm Word
venue-2 u m mm MD
I»: um In Is sa vs a
Figure we III-ck control wont
Eflflmflflflfl
—]: IDENTISIBMIEMIIW
mm won
um we
I» . a new" Imus
n. . r mm" EMILE
Flume ll. lnl‘lrum Dis-Me Wold
7|
PS018001-0602
PIN DESCRIPTION
PMAF Port A Bus (btdrectional. Smile). This 8-bit bus
transleis data. status, 01 COMIC! Inivrmatlon Mn MA
at the Flo and a periphelal device. Pkg is the least
SIQHIW‘ bit 01 the PortA data bus.
ARDV. Register A Ready (output. active High), The
meanlng bi this stgnel depends on the mode at operation
selected tor PbrtAas Iollows:
Output Mod-r This Signal goes active to indicate that the
Poll A output register has been loaded and the peripheral
data bus ls stable and ready lot lranstel to the peripheral
device.
Input Mode. This etgnal Is active when the Port A Input
register is empty and ready to accept data train the
peripheral device.
Bidirectional node. The signal is active when data is
available In the Pen A output register tor tmnster to the
peripheral devtoe. In this mode. data is not placed on the
PortAdata bus. unless AS—TB isaetive.
Comm! "Odo. This stgnal is disabled and towed to a Low
stale.
A515. Poll A Strobe Pulse From Feliphers/ Device (lnpul.
active Law). The meaning cl this signal depemls on The
mode OI operation seleded Io! PonA as blows:
Output Mode. The posllive edge at this strobe is Issued by
the penpherel to acknowledge the rebeipt 01 data made
available byihe Pto
Input Mode. The strobe Is issued by the petipheral ID load
detatrbrnthewwu mtoihePottA inputregister. Datais
loaded into lite PIO when lhls etgnal Is active.
Bid/notional Mode. When lhis signal is active. data horn
the Port A output register is galed onto the Pen A
bldirectlonal data bus. The positive edge 0! me §TODe
acknowledges the receipt ol the data.
Comm/Mm. The strobe is inhithBd Internally.
P594157. Poll B Bus bidirectional. Genie). This 51:11 bus
translers data. saws. or control Information between Port B
anda peripher device. The PottB date buscan suppiyt s
"m at I 5V to dnve Darlingtnn transistors P50 is the least
signilieani bll at the bus.
BIA. Rm 3 or A Select (lnpul, High - at. This pln defines
which port ts mama during a data tlanster between the
cpu and the Pie. A Low on this pin selects Port A: a High
Selects Purl E. Otlen endless btlAglrom the CPU is used Io!
IhlS selection lunctiari
annv. Register 5 Ready (output, active High). This Signal is
smile! to ARDY. ewepllhel in the Port A bidirectional mode
this signal is High when the Port A input register is empty
and ready to accept data horn the peripheral device
BSTB. Pull B Snobe Pulse From Penphelal Device finput.
awve Lw). This signal is slmilar to m. except that in the
Port A btdiiectiorial mode this Signal strobes data lrom the
peripheral devtce into the Port A input register,
an"). Control or Date Select (lnpul, High = C). The pin
delines the type 0! data translei to be perlorrned between
the CPU and the PIO. A High ohthis pin during aCPU write
to the PIO causes the 230 data bus to be imeipreted as a
commandlot the port selected bythe BIA Selecl line. A new
on this ptn means that the 280 data bus is belrlg used to
translet data between the CPU and the PIO. Onen address
bit A. lrorn the CPU is used loi this Iuncllon.
OE. Chip Enable (input. active Law). A Low on this pin
enables the PIO In em mmand 0! data Inputs ITDm me
CPU timing 3 Mite cycle or to transmit data to the CPU
dulirtg a Teen cycle. This Signal ts genevally decoded lrom
hurl/O port numbers Io! Form A and B. dew. and control
CLK. System Clock (input). the Z30 PIO uses lhe Qanclard
slnglephase 280 system clock.
Dray. zsuCPu Data Bus (bdirecttonal, 3~state). This bus is
used ID transler all data and commands between the 150
CPU and the 230 FIG. DD is the least significant blI.
IEI. Interrupt Enable in (input, active ngh). This signal is
used to term a pimy-imerrupt daisy chain when male than
one interrupt dTIven deylbe is being used A High level on
this ptn indicates that no other Ciel/Ices at higher plmllly ale
being serviced by a CPU inteirupt servtee routine
IEO. interrupt Enable Out (output. active ngh). The IEO
signal is the other 5ng Tequired to term a daisy chain
prionty scheme ll is Htgh Ody TI IEI is High and Ihs CPU is
not servicing an interrupt Irom this Plo Thus this stgnal
mocks Imwelpllolitydevbesltom interrupting while ahlgher
pTIOMy Gel/Ice Is belng serviced by Its CPU Interrupt service
routine.
ltTT. Influpl Request (output. open drain. active Law)
When INT is active the 230 no is requesting an iniernipt
Item the zso CPU.
Iona. In i/oiitput Request nnput horn gee c_Pu._acliiie
Law). I is used in boniunetion with BIA. CID. CE. and
filo lransler oommandsjnd data betfln the no CPU
and the zero PIO. When CE, lain, and lORO are active. the
port addressed by BIA transters datafle CPU (a Tead
ggeralion) Conversely when E and IORO are auive but
RD is net. the port addressed by EVA is written into [tom the
CPU with either data or cfltllol inlorrnation. as spedllied by
0/5. Atso. ii W2 and Mt are atmve simultaneously. the
CPU is acknawtedging an interrupt, the tnterruplihg port
automaticalfy places its interrupt veclolonthe CPU data bus
ilit is the highest priority device requesting an interrupt
PS018001-0602
Ml. MachineCyoleonpuI iiom CPU active Low) This stgnal
ts used as a sync putee Iyanlm! several internat PIO
operations When both the Mi and W signals aie active.
the 230 CPU is ieiehing an ins1wcllon iiom memory
Convasety. when mm m and IORQ ate give, ihe CPU is
acknoMedging an anieinipt, In addition. Mi has Iwo other
«unmiohs within the 230 PIO it synchronizes the Pie
inteuupt logic; when W oecuis wnhaut an active W) or
IOHO signal, ine Pio‘istesei.
R— ReadCycte Status (input tram 230 CPU. acnve Lmt), it
E ts actwe, or an l/O ofllon is in DngVeSs, TB is used
wllh 3/5. 0/5, CE, and IORQ to uansiei data horn ihe 280
no (0019230 CPU
TIMING
The ioiiouing timing aiagiahis show Iyplcsl timing in a 230
CPU envnonmeni, For more piecise speciticaiions ieiei lo
the eomposne ac tuning diagram,
Wlilfl Q/cle. Figure 12 illustiates |he llmlng [0'
programming the 290 FIG oi toi wnllng data to one at its
ports The PIO does net ieceive a specmc wine signal;_it
internatly generates tts own train the lack 00 an active RD
5|ng
Read welet Figure 13 iiiustyates the Ilmlng iai leadlrlg the
data Input "om an external Get/toe to one 0' (he ZBO PIO
ports
Output Made (Mode 0). An output cyeie (Flgure i4) is
always startedjy the executton at an output ins11ucllon by
the CPU TheWR' pulse iiom theCPu latches the data ltom
th_e CPU data bus into the selected Don'soulpm regisiei. The
wn‘ putse sets the Ready nag ener a Lowgomg edge oi
CLK‘ Indicating data ls available Ready stays Scllve until the
positive edge at the strobe line is leoetved, indicating that
data was taken by the penphelal. The pastime edgeoi the
stiebe putse geneiatesan Wit the interrupi shame in-iiop
has been set and it this device has the highest piionty
1i r, V... r. v.
'm-nea-wm—t
Fume 12. Wm. Cycle Tlmtng
5.‘ E
i:
mm:
m
~us.ns.fi.w.m
Funnilmcyde nintng
m—————\_
name at Mode 0 output ‘nintiig |
73
PS018001-0602
Input Mane (Mod- 1) When STROBE goes [tam Law to
Htgh data ls latched unto the setected pott unput uegisteu
(Figute 15) Whule STROBE usLow the unput data latches ate
transparent The next tusungedgeolsT ROBE acttvates |_NT ul
lntenupt Enable us set and this us the htghest-prlorlty
uequestung dewce Thetotlowing tallung edge at CLK resets
Headyto an lnacllve state tndtcattng that theunput teguster ts
tull and cannot accept any more data unlll the CPU
completes a read When a read us complete the posmve
edge at E) sets Ready at the next LowAgotrtg tuansutuon ol
CLK At thus ttme new data can be loaded unto the PIO
nnnv
Eldltecfloml Mode (Mad. 2). Thus Is a comNnaIIon 0!
Modes 0 and 1 usung all but handshake tunes and the etgtut
Port A no tunes (Figure I6). Pan B mus1 be set to the btl
mode andns Inputs muSl bemasted. The PonAhandshake
tunes are used bf 0u|put COMIOI and the Poll 8 ltnes ale
used to: unput oontuol ll tnlerrupts 00cm, Port At vector wull
be used dunng Don output and Port B's wtll be used durlng
pout Input Data us allowed out onto the Fun A bus only when
ASTB ts Law The uustng edge or thus strobe can be used to
latch the data We the penphetal
thuun ts. Mode 1 tnput Ttmlng
cut
’ \uu_/uetn \
um uu
um I
”41L
‘fixln-fi-W~fi
thunu ts. Mods 2
statmcuon-u 'nuuutng
74
PS0018001-0602
not Control Itlode (Mode 3). The M mode does not utttize
the handshake signals, and a normal port wrrte or part read
can be executed at any time. When writing, the data is
latched into the output registers with the same timing esttte
oulpu| mode.
When reading (Figure 17) the PIC, the data returned to the
CPU ts composed cl output register data {tom those port
data lines asstgned as outputs and input register date lrurn
those pen data lines assigned as tnputs The input register
contains data that was present trrirrtedielety prior to the
tatling edge at FT) An interrupt is generated it tnlerrupls
Item the port are enabled end the date on the port data lines
Sa|l51y the logical aquatton defined by the 8-hll mask and
2-bit mask conltctl registers However. it For! A is
programmed tn Ddl'eOltOflalfllDde, PMBdDe‘SDDI issue an
interrupt in ct mode and must theretore be potted,
Interrupt mom-age Tlmlng. During m time,
pertphetal mm are inhieaed trcrn changing their
interrupt enable statue. permitting the interrupt Enable
sgnal to ripple through me daisy chatn The peripherat wtth
lEl High and IEO Low dunng INTACK places a
pteptogiammed 8-minterruptvectoron the data bus atthis
time (Flgure ta). tee is held Law until a Return Ftom
Interrupt (FIETI) insuuctton is executed by the CPU while IEI
is High The 2-pyte RETI mstructtcn is decoded Inlemally by
the PIO tor this purpose.
Return From interrupt 01*. It a 230 penphetzl has no
interrupt pending and ts not under servtce, then ta IEO -
IEI, it it has an interrupt under serytce tie, it has already
interrupted and received an imanupl acknowledge] then ts
IEO IS always Low, inhibttng lower priority deyices trcrn
interrupting it it has an interrupt pending which has not yet
been acknowledged. IEO is Law unless an “ED" is decoded
as the met [7er 01 a 2-t7yte cocode (Figure 19) in this case.
IEO goes High until the next cpccde by|e is decoded,
whereupon II goes Law again. It the second [Me at the
opcode was a "40," then the opcode was an RETI
Insflucllort
Atter an "ED" opcode is decoded. only the peripheral
device which has interrupted and is currently under service
has its lEl High and its IEO Law. This device is the
highestpriarity devtce in the daisy chain that has Iecetved
en internrpt ackmmedge All other pencherals have tEi =
IEO llthe next opcode {7er decoded can." this peripheral
device resets ts "interrupt under sen/ice~ condition,
a
man an"... autumn x
W M'Aflavcx
were;
RT:
IE
it... a...
[hummmmm
Flgun "t ”04035“ Cnnlml Mod- 11mlng, Bil Mada Run
“1",,“ I .u r. r, r, r. v. t. r. r. r.
M m
m
- .1?“ m —\_/—\__/—
..
— _/— :m "- \.__/ \__/
m fl——Iaren‘t:tenet.
.1 w
..
...
Figure 1a. Interrupt Acknowledge nrrilrrg
Flgun 19. Rotum From Interrupt
75
PS018001-0602
ABSOLUTE MAXIMUM RATINGS
Voltages on voc wtth tespemo v55 .-O.3Vlo + 7.0V
Voltages an all inputs wilh respec
tovss. . , . -oavmvcc+oav
Stolage Tempera ure . . ,765°C to +1so°c
sum gtmtttm lhoseltied m Amman Maxmum mugs mly
ms- pennant: maps In In: W m: IS A mass mung oliy,
opeunon a the m 51 any women nbme Inca mm "I ma
comma: ms at these specmwtms Is not unwed Exposure (0
mm: manmum mm muons .01 mm gum may amen
demos tummy
STANDARD TEST CONDITIONS
The characteristics below appty (or me tonowtng test
oonattions, unless olhelwise noted. All voltages are
lelelenoed 10 GND (0V), Posttws when! news no me
relelenced pin. Avauable operattngtempetatme range IS.
I S=O'Clo+10'c.vgnunoo
NMOS: «Jsvgvm s «525‘!
CMOS: .4 50vng 5 s5 50v
l E: 40‘C IO Im‘ +4.50V SVDCS OSVSOV
The Ovdeling lnIormalIon seem" hats package tempetamte
ranges and pvoducl numbels Heterto me Lttetatute Ltst «or
additional dooummallon. Package dvawmgs are In lhe
Package lnIotmatIon section
45v
zyx
mm 00m"
wont 1231
m1
no
.4
CAPACITANCE
51M Pm!
c dock cap-chance
Cm Input Capacitance
Gout Ompulcapmnsnoe
MWMWNIWI- um;
Ummummmwvtm.
76
Min MIX Uull
10 m
15 W
PS018001-0602
DC CHARACTERISTICS WON/00406 230 Flo)
V0550] : 10%, unless mhemse speclnea
Symbol PW Min Max Typ Unit Common
Vu: Hock Inpul LOW Voltage -O.3 +0.45 V
vm Clock Inpul High Vollage Vac—0,6 Veg-0.3 v
v, Input High Voltage 2 2 vDc v
V" Input Low Voflage 03 08 V
V41 UUIDUI LOW Vollage O 4 V
v0," Oulpul High leage 2 4 v
Vm7 Oulpul High Voltage Vac-0.8 V
I” mum Leakage Curvenl 710 10 uA
ILo 3-Slale Outpul Leakage .10 10 "A
- Cunenl in Floal
lac. Power Supply Cunenl - 4MH1 5 2 mA vcc=5v
> MHz 6 MA CLK=4,G,8,WHZ
- mm 7 mA vnwwo 2v
‘ - IoMHz I2 mA V60 2V
um Standby Supply Currenl 00 o 5 M vw=5v,
CLK— 0)
vnzvoco 2v
vl=02v
Ian Daninglon Drive Culrenl 4.5 -5.0 mA szl 5V
[Povl a Only) REX1 - .IK ohm
mu:
m Wmmmumw
PS018001-0602
AC CHARACTERISTICS (ZMCZOICMOS 280 PIO)
28402004' 2840M 28402008 23402010 Mole
No Sylltol PW Mn Max Mh Max Mil Max IE1 Max
I lcc kaCycle Time 250 [l] 162 [l] l25 {l} loo [I]
2 Ian Clock Pulse Widlh (High) 1 lo DC 65 DC 55 DC 42 DC
a TwCl Clock Pulse Wldlh (Law) 110 DC 65 DC 55 DC 42 DC
4 no Clock Fall Time 30 20 I0 10
5 nC Clock Rise Time 30 20 lo 10
6 IsDSlRI) ICES/[ACID lo (RD, [IORQ Fall 50 50 40 35 tel
Selup Time
7 In Any Hold limes I01 Specilled AD 35 15 ls
Setup time
8 Tslil(cl IRD, /IORO to Clock Rise Selup Iime 115 70 so 40
9 IaRllDOi (RD. AORQ Fall lo Dala Oul Delay 380 300 200 120 12]
10 ldelDOs) IRD. AORO Rise [0 Dala Out 110 70 60 50
Flea! Delay
1 I TSDKC) Data In lo Clock Rise Seluo Time 50 4D 30 20 CL=50DF
l2 laloluol) IIORQ Falling loDala Oul Delay 160 120 80’ 80 [3|
(INIACK Cycle)
13 lle(Cr) /Ml Falling lo Clock Rlsmg 90 70 50 4o
Selup Time
M lsMIlcl) [Ml Fall lo Clock Rise Selup Time 0 o 0 ,20
(IM1 Cyclel
l5 TdMlllEO) [Ml Fall l0 IFO Fall Delay
(lnlelrunl Immedialely Preceding ml) 100 70 70 [5.7]
[MI Fall)
l6 Tlel(l0) IEI to none Falling Selup Tune MD loo 80 60 [7!
(IINTACK Cycle)
17 leEKIEOl) IEl Fall lo IEO Fall Delay I30 l20 70 7o [5)]
la leElllEOr) lEl Rise lo IEO Rlse Delay |60 I50 70 7o Cl=500F
19 TclO(C) IIORO Rise to Clock Fall Selup Time
(To Acllvale RDY on Nexl Clock Cycle) 20) 170 140 I20
20 TdC(RDVr) Clock Fall lo RDV Rise Delay 190 170 150 130 [5].
CL =5ODF
21 lclclHDvll Clock Fall to RDY Fall Delay 140 I20 loo 85 5)
22 TwSTB ISYB Pulse Wldlfl 150 120 IUD 80 [41
23 TsSTHC) [SIB Rise lo Clock Fall Setup Time
(1 o Activate my on Nexl Clock Cycle) 220 lso 120 100 5.]
2d lle(PD) /lono Rise In Purl Dala Slable Delay 180 lea 140 ‘20 [5|
(Mode 0)
25 TsPD(STB) Porl Dala l0 [ST B Rise Selup Time 230 190 I40 75
(Mode l)
26 TdSTBlPD) ISIS Fall lo Poll Dala Slable (Mode 2) 2l0 18C! lho 120 [ill
‘4 MHz CMOS 84020 Is Obsoleted and Ieplaced by 6 M lz,
78
PS018001-0602
134w Ac CHARACTERISTICS (Continued)
Z8402004'284C2006 28462008 28402010 Mme
N0 Symbol Pumr Mil Max Mh Max W» Max Min Max
27 IdsTB(PDr) /sTB Rise to Povl Dale Float Delay 130 160 ‘40 120 CL=SODF
Wade 2)
28 fdPD(lNT) Porl Data Malch Io [INT Fan Delay 490 430 360 200
(Mode 3)
29 TdSIBuNT) 1313 Rise to [INT Fall Delay 440 350 29 220
- umhm‘man-aw,
:4: MHz 284030 IS 0050112156 and replaced by 6 MHz
m:
"I I‘m—ma. whammm
[21 melbyImhmwmmlnwwlon
[a] mmuDOowmsthha—dnghLo-iwhmqu
[4] F91 Mad. 2 “magmas;
[5| mmmwmhr‘mnumhmwmwm
[a] ”manly my». «am. mm". m. um. um mnwnnwul be m b Mame).
[71 25rd > (N-zfldlEKIEG) . Tmlquy dunno) . m m may. it .w,
[a] mmh..momnimmmmmnommum.
Dc CHARACTERISTICS (W08 280 Ho)
Symbol mum: mu lax unn m1 cannula"
VI“; Clock Ianoonnage —03 +045 v
vm clockinmflvwonaoe Vac—06 vocnm v
VIL InpulLodeligs ~03 90.8 v
v." Input High Wings + 2 o Vcc v
VOL mmwmw +0.4 v 40L - 2,0mA
v0" want-«among; m4 v lo“ : —250uA
IU InputLaakageCunem 110 M v." = DIoVoc
Im 38m 0am Leakage Cunemm Flom :10 M vow - o 4VlaVcc
'00 Pm Sandy Current 100 mA
loan Damngmn Dnva Cunem — I 5 M v0" = 1.5V
Pan 5 Only Rex! = 390 9
mu summed mneramm and mugs vanoe
79
PS018001-0602
M: CHARACTERISTICS? (28420041403 280 Flo)
WWW
III-mm swam mm am In uIn Mu mm:
1 10c ClockCydeTAme 250 {1] 132 [1]
2 Mn Clock wmn (Higm 105 2000 55 2000
3 m1 Clock W1dth1Low) 105 2000 55 2000
4 no Clock Fall Time so 213
5 TIC mock Rise Tlme :10 20
6 TsCS(RI) 313/5105 In W. WI Setup Tune so 50 [6)
7 1'11 Any Hdd fimtovSpecmeanupnme o o o
a mum) W.mm0|oddsaiupfime 115 70
9 wanna) E. m 1 lo um om Delay am: 300 [2]
10 1de¢DOsD filimmmomnou Delay no 70
11 1501(5) Dulnmcbckosmpnm so 40 CL- 5091
12 memo» mmnmmoaayumwx Cycle} 200 12a [3]
13 TsM1(CI) Whouockvsevuprm 90 70
I4 homer; W maooktsaupnmeofl cm) 0 o [a]
«5 TdMIaEO) W 4191501 Delayflmefmmlmmeaatdy
Pveceaingm I) 190 100 15.71
16 memo) IEI lo We 1 Setup 'fims annex away 140 100 m
17 TdIEIflEOY) 151 Mo 1501 Delay 130 120 (5]
muwm
1a Manson IE! m 1501 Delay (alter ED Decade) 160 150 [5]
19 mom) WrmmmlwupnmmMWE
Won mckayae) 200 no
20 mommy) Clock 1 to Rm 1 Dday 190 170 [51
CL - 50 D1
21 momma dedmREAmlDeiay 140 120 [s]
22 m SW Puss man «so 120 I4]
23 Esme) Wmcmusmupnmeaomm
REAL" on Next Clock was) 221) 150 15]
24 moms) 10170 1 m PORT mu smug Dewy {Mode 0) 190 160 [5]
25 790511?) Pommmwmrsmpme (Modeu 230 190
26 Tasman» W Ho PORT DATA Stable (Mode 2) 210 130 [51
27 Tasman) Wrmmmom Float Dem/(Mode?) 130 150 CL a 50m
23 mmmn Pom DATA Mam: 1.2 W: Delay (Mode 3) 490 430
29 Tasman» W 1 to NT 1 0918111 440 350
MOVES
[Ijflxi = INCH 4 TMJI 6 WC 4 "C |511mmasemvahesw2mbreachIommaaasemmnu uplo
[mm-urofitmowwmsmmsavmuwmmupm 100mm“
200 sum [a] man" my m reduced um um lune subvamed cm msmn
[allmuHlemDODD/ lunslovfiachsfl PI, mmlnmm uu|o Mmmmwrdfiknoj.
ZWMM 'M‘muubem‘mlmmumMMCMO/des|owflwl7l0
[41511411592 msraflsmsrmr mus-n mmustnsv
PS018001-0602
AC TIMING DIAGRAM
emu
ml. an
:4
SI
our
nuav
mum on mm
min on my
nous.
um:
..
8|
PS018001-0602
PS018001-0602
Customer Support
For answers to technical questions about the product, documentation, or any other issues
with Zilog’s offerings, please visit Zilog’s Knowledge Base at http://www.zilog.com/kb.
For any comments, detail technical questions, or reporting problems, please visit Zilog’s
Technical Support at http://support.zilog.com.
