FEATURES 1MHz Clock Rate SPI Modes x 8 Bits --16 Byte Small Sector Program Mode Low Power CMOS --<1�A Standby Current --<3mA Active Current during Program --<400�A Active Current during Read or 5V "Univolt" Read and Program Power Supply Versions Block Lock Protection --Block Lock Protect 0, any 1st 1/2, First or Last Sector of SerialFlash Array Built-in Inadvertent Program Protection --Power-Up/Power-Down Protection Circuitry --Program Enable Latch --Program Protect Pin Self-Timed Program Cycle --5ms Program Cycle Time (Typical) High Reliability --Endurance: 100,000 Cycles/Byte --Data Retention: 100 Years --ESD: 2000V on all pins 8-Lead SOIC Package 8-Lead MSOP Package 8-Lead TSSOP Package 8-Pin Mini-DIP Package FUNCTIONAL DIAGRAM

The is a CMOS 4K-bit SerialFlash, internally organized x 8. The X25F047 features a Serial Peripheral Interface (SPI) and software protocol allowing operation on a simple four-wire bus. The bus signals are a clock input (SCK) plus separate data in (SI) and data out (SO) lines. Access to the device is controlled through a chip select (CS) input, allowing any number of devices to share the same bus. There are eight options for programmable, nonvolatile, Block Lock Protection available to the end user. These options are implemented via special instructions programmed to the part. The X25F047 also features a PP pin that can be used for hardwire protection of the part, disabling all programming attempts, as well as a Program Enable Latch that must be set before a program operation can be initiated. The X25F047 utilizes Xicor's proprietary Direct WriteTM cell, providing a minimum endurance of 100,000 cycles per sector and a minimum data retention of 100 years.

PIN DESCRIPTIONS Serial Output (SO) is a push/pull serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock. Serial Input (SI) is a serial data input pin. All opcodes, byte addresses, and data to be programmed to the memory are input on this pin. Data is latched by the rising edge of the serial clock. Serial Clock (SCK) The Serial Clock controls the serial bus timing for data input and output. Opcodes, addresses, or data present on the SI pin are latched on the rising edge of the clock input, while data on the SO pin change after the falling edge of the clock input. Chip Select (CS) When CS is HIGH, the X25F047 is deselected and the SO output pin is at high impedance and unless a nonvolatile write cycle is underway, the X25F047 will be in the standby power mode. CS LOW enables the X25F047, placing it in the active power mode. It should be noted that after power-up, a HIGH to LOW transition CS is required prior to the start of any operation. Program Protect (PP) When PP is LOW, nonvolatile writes to the X25F047 are disabled, but the part otherwise functions normally. When PP is held HIGH, all functions, including nonvolatile writes, operate normally. PP going LOW while CS is still LOW will interrupt a programming cycle to the X25F047. If the nonvolatile write cycle has already been initiated, PP going low will have no affect on this cycle. PIN NAMES Symbol SO SI SCK PP VSS VCC NC Description Chip Select Input Serial Output Serial Input Serial Clock Input Program Protect Input Ground Supply Voltage No Connect

PRINCIPLES OF OPERATION The x 8 SerialFlash designed to interface directly with the synchronous Serial Peripheral Interface (SPI) of many popular microcontroller families. The X25F047 contains an 8-bit instruction register. It is accessed via the SI input, with data being clocked in on the rising edge of SCK. CS must be LOW and the PP input must be HIGH during the entire operation. Table 1 contains a list of the instructions and their opcodes. All instructions, addresses and data are transferred MSB first. Data input is sampled on the first rising edge of SCK after CS goes LOW. SCK is static, allowing the user to stop the clock and then start it again to resume operations where left off. Program Enable Latch The X25F047 contains a "Program Enable" latch. This latch must be SET before a program operation is initiated. The PREN instruction will set the latch and the PRDI instruction will reset the latch (Figure 4). This latch is automatically reset upon a power-up condition and after the completion of a sector program cycle.

Block Lock Protection There are eight Block Lock Protection options. The predefined blocks and associated address ranges are protected by programming the appropriate two byte Program Status instruction to the device (Table 1 and Figure 6). Once a Block Lock protect instruction has been completed, that Block Lock Protection setup is held in a nonvolatile Status Register (Figure 1) until the next Program Status instruction is issued. The sections of the memory array that are Block Lock protected can be read but not programmed until Block Lock Protection is removed or changed. Figure 1. Status Register/Block Lock Protection Byte 0 BL0 clocks. CS must go LOW and remain LOW for the duration of the operation. The host must program 16 bytes in each write with the restriction that these bytes reside on one sector. If the address counter reaches the end of the sector and the clock continues, or if fewer than 16 bytes are clocked in, the contents of the sector cannot be guaranteed. For a sector program operation to be completed, CS can only be brought HIGH after bit 0 of the last data byte to be programmed is clocked in. it is brought HIGH at any other time, the program operation will not be completed. (Figure 5) Read Status Operation If there is not a nonvolatile write in progress, the Read Status instruction returns the Block Lock Protection byte from the Status Register which contains the Block Lock Protection bits BL2-BL0 (Figure 1). The Block Lock Protection bits define the Block Lock Protection condition (Figure 1 and Table1). The other bits are reserved and will return "0's" when read (Figure If a nonvolatile write is in progress, the Read Status instruction returns the status of the internal write operation on SO. When the nonvolatile write cycle is completed, the status register data is again read out. During a nonvolatile write in progress, the SO pin will be set HIGH. At the end of the nonvolatile write cycle, SO is set to output the current bit from the status register. Clocking SCK is valid during a nonvolatile write in progress, but is not necessary. If the SCK line is clocked, the pointer to the status register is also clocked, even though the SO pin shows the status of the nonvolatile write operation (Figure 3). When the pointer reaches the end of the eight bit status register, it "rolls over" to the first bit of the register. Program Status Operation Prior to any attempt to perform a Program Status Operation, the PREN instruction must first be issued. This instruction sets the "Program Enable" latch and allows the part to respond to a Program Status sequence (Figure 6). The Program Status instruction follows and consists of one command byte followed by one Block Lock Protection byte (Figure 1). This byte contains the Block Lock Protection bits BL2-BL0. The rest of the bits [7:3] are unused and must be programmed as "0's". Bringing CS HIGH after the two byte Program Status instruction initiates a nonvolatile write to the Status Register. Programming more than one byte to the Status Register will overwrite the previously programmed Block Lock Protection byte (Table 1).

Read Sequence When reading from the SerialFlash memory array, CS is first pulled LOW to select the device. The 8-bit READ instruction is transmitted to the X25F047, followed by the 16-bit address, of which the last 9 bits are used (bits [15:9] specified be "0's"). After the READ opcode and address are sent, the data stored in the memory at the selected address is shifted out on the SO line. The data stored in memory at the next address can be read sequentially by continuing to provide clock pulses. The address is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address is reached (01FFh), the address counter rolls over to address 0000h, allowing the read cycle to be continued indefinitely. The read operation is terminated by taking CS HIGH (Figure 2). Sector Program Sequence Prior to any attempt to program data into the X25F047, the "Program Enable" latch must first be set by issuing the PREN instruction (Table 1 and Figure CS is first taken LOW. Then the PREN instruction is clocked into the X25F047. After all eight bits of the instruction are transmitted, CS must then be taken HIGH. If the user continues the program operation without taking CS HIGH after issuing the PREN instruction, the program operation will be ignored. To program data to the SerialFlash memory array, the user then issues the PROGRAM instruction, followed by the 16 bit address of the first location in the sector and then the 16 bytes of data to be programmed. Only the last 9 bits of the address are used and bits [15:9] are specified be "0's". The entire write operation takes 152