Part | U62256AS2A07LL |
Category | |
Description | Standard 32K X 8 SRAM |
Company | ZMD |
Datasheet | Download U62256AS2A07LL Datasheet |
Features, Applications |
Features ! 32768x8 bit static CMOS RAM ! Access times 70 ns, ns ! Common data inputs and Description The is a static RAM manufactured using a CMOS process technology with the following operating modes: - Read - Standby - Write - Data Retention The memory array is based a 6-transistor cell. The circuit is activated by the falling edge of E. The address and control inputs open simultaneously. According to the information of W and G, the data inputs, or outputs, are active. In a Read cycle, the data outputs are activated by the falling edge of G, afterwards the data word read will be available at the outputs DQ0-DQ7. After the address change, the data outputs go High-Z until the new information read is available. The data outputs have not preferred state. The Read cycle is finished by the falling edge or by the rising edge of E, respectively. Data retention is guaranteed down 2 V. With the exception of E, all inputs consist of NOR gates, so that no pull-up/pull-down resistors are required. ! Three-state outputs ! Typ. operating supply current70 ns: mA 100 ns: mA ! TTL/CMOS-compatible ! Automatical reduction of power dissipation in long Read Cycles ! Power supply voltage 5 V Operating temperature ranges QS 9000 Quality Standard ! ESD protection 2000 V (MIL STD M3015.7) ! Latch-up immunity mA ! Packages: PDIP28 (600 mil) SOP28 (330 mil) Signal Description Address Inputs Data In/Out Chip Enable Output Enable Write Enable Power Supply Voltage Ground Truth Table Operating Mode Standby/not selected Internal Read Write- DQ7 High-Z Data Outputs Low-Z Data Inputs High-Z All voltages are referenced to VSS 0 V (ground). All characteristics are valid in the power supply voltage range and in the operating temperature range specified. Dynamic measurements are based on a rise and fall time of 5 ns, measured between 10 % and % of VI, as well as input levels of VIL 0 V and VIH 3 V. The timing reference level of all input and output signals 1.5 V, with the exception of the tdis-times and ten-times, in which cases transition is measured �200 mV from steady-state voltage. Absolute Maximum Ratings a Power Supply Voltage Input Voltage Output Voltage Power Dissipation Operating Temperature C-Type K-Type A-Type C/K-Type A-Type Stresses greater than those listed under ,,Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability Maximum voltage 7 V Not more than 1 output should be shorted at the same time. Duration of the short circuit should not exceed 30 s. Recommended Operating Conditions Power Supply Voltage Input Low Voltage d Input High Voltage |
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