Versatile IC supports 155/51 Mbits/s SONET/SDH interface solutions for DS2, T1/E1/J1, and DS0/E0/J0 applications. Implementation supports both linear (1+1, unprotected) and ring (UPSR) network topologies. Provides full termination 28 J1. Low power 3.3 V supply. +85 �C industrial temperature range. 456-pin ball grid array (PBGA) package. Complies with Bellcore, ITU, ANSI, ETSI and Japanese TTC standards: GR-253-CORE, GR-499, (ATT) TR-62411, ITU-T JT-G707, JT-I431-a, ETS 300 4171-1, ETS T1.107, T1.404.

Interprets STS/AU/TU-3 pointers. Synchronizes 8 kHz frame and 2 kHz superframe to system/shelf timing reference by setting the transmit STS-3/STM-1 pointers to a fixed value of 522. Monitors/terminates SPE path overhead.

Telecom bus interface to mate devices including clock, data[8], parity, SPE-, J0-, J1-, and V1 timing indicator. Line and path RDI and REI signals passed to mate devices. Three super mapper devices, two configured as mate devices, provides full termination STS3/STM-1. A three chip solution to terminate 63 E1s.

Termination of a single 155 Mbits/s STS-3/STM-1 or single 51 Mbits/s STS-1/STM-0. Built-in clock and data recovery circuit at 155 Mbits/s STS-3/STM-1 interface (can be deselected if external clock recovery is provided). Supports overhead processing for all transport and path overhead bytes. Optional insertion and extraction of overhead bytes via a serial transport overhead access channel. Configurable as dedicated DCC channels. Software controlled linear 1+1 protection via dedicated interface to protection card. Full path termination and SPE extraction/insertion. SONET/SDH compliant condition and alarm reporting. Built-in diagnostic loopback modes. 8 kHz line frame sync output.

Monitors/terminates VT path overhead for 21 VT2/TU-12. Synchronizes VT/TU SPE to system/shelf timing reference by setting the transmit VT/TU pointers to fixed values for asynchronous mapping or by dynamically changing the transmit VT/TU pointers for byte synchronous mapping. Fixed pointer generation in transmit side for asynchronous mapping. Dynamic pointer generation in transmit side for byte-synchronous mapping.

Features................................................................................................................................................................... 1 SONET/SDH Interface....................................................................................................................................... 1 STS/STM Pointer Interpreter............................................................................................................................. 1 Telecom Bus Interface....................................................................................................................................... 1 VT Termination/Generation (x28/21)................................................................................................................. 1 Mapping/Multiplexing Modes 21 M13 Features.................................................................................................................................................. 21 DS3/DS2/DS1/E1 Cross Connect................................................................................................................... 21 Jitter Attenuation............................................................................................................................................. 21 PDH Interfaces................................................................................................................................................ 21 T1/E1/J1 Framing Features (x28/21).............................................................................................................. 21 System Test and Maintenance....................................................................................................................... 22 Microprocessor Interface................................................................................................................................ 22 Chip Testing and Maintenance....................................................................................................................... 22 Interface to Other Lucent ME Devices................................................................................................................... 22 Preface.................................................................................................................................................................. 23 Introductory Sections...................................................................................................................................... 23 Functional Sections......................................................................................................................................... 23 Characteristics Sections................................................................................................................................. 23 Parts that Make Up the Functional Sections................................................................................................... 24 Naming Convention for Registers and Parameters......................................................................................... 24 Overview................................................................................................................................................................ 25 Application Diagrams...................................................................................................................................... 26 High-Speed Line Interfaces and Clock and Data Recovery............................................................................ 27 STS-3/STM-1 Overhead Processing.............................................................................................................. 28 Multiplex Section Protection (MSP 1+1)......................................................................................................... 29 Pointer Interpreter........................................................................................................................................... 29 Path Termination Function.............................................................................................................................. 29 STS-3/STM-1 Mux-Demux.............................................................................................................................. 30 Telecom Bus Interface--Interfacing to Mate Devices..................................................................................... 30 SPE/AU-3 Mapper (DS3 Mapper)................................................................................................................... 30 VT/VC Mapper................................................................................................................................................ 31 M13/M23 Multiplexer....................................................................................................................................... 32 Cross Connect Block...................................................................................................................................... 33 Digital Jitter Attenuator.................................................................................................................................... 34 Test Pattern Generator................................................................................................................................... 34 28 Channel Framer......................................................................................................................................... 35 Line Decoder/Encoder.................................................................................................................................... 40 Receive Frame Aligner/Transmit Frame Formatter......................................................................................... 40 Receive Performance Monitor........................................................................................................................ 40 Signaling Processor........................................................................................................................................ 41 Facility Data Link (FDL) Processor................................................................................................................. 41 HDLC Unit....................................................................................................................................................... 42 System Interface............................................................................................................................................. 42 Pin Information...................................................................................................................................................... 43 Microprocessor Interface and Super Mapper Global Control and Status Registers.............................................. 71 Introduction..................................................................................................................................................... 71 Features.......................................................................................................................................................... 71 Microprocessor Interface................................................................................................................................ 71 MPU Block Diagram........................................................................................................................................ 72 Super Mapper Register Address Mapping...................................................................................................... 73 Performance Monitoring (PM) Counters Operation......................................................................................... 74 2 Lucent Technologies Inc.

Super Mapper Global Interrupt Status and Control.........................................................................................75 Global Control..................................................................................................................................................75 Super Mapper Global Control and Status Register Descriptions.....................................................................76 Microprocessor Interface Register Map...........................................................................................................86 Microprocessor Interface Register Map...........................................................................................................87 TMUX Functional Description................................................................................................................................88 TMUX Introduction...........................................................................................................................................88 TMUX Features...............................................................................................................................................88 TMUX Receive Path Overview........................................................................................................................89 TMUX Transmit Path Overview.......................................................................................................................91 TMUX High-Level Block Interconnect Diagram...............................................................................................93 TMUX Detailed Block Diagram........................................................................................................................94 Receive Direction Functional Block Diagram...................................................................................................95 Receive Direction (Receive Path from Sonet Global/SDH).............................................................................96 Transmit Direction (Transmit path to SONET/SDH line)................................................................................116 TMUX Register Descriptions.........................................................................................................................128 TMUX Register Map......................................................................................................................................185 SPE Mapper Functional Introduction....................................................................................................................................................194 Features.........................................................................................................................................................194 SPE Mapper Functional Description (continued)...........................................................................................195 SPE Mapper Functional Block Diagram........................................................................................................195 Basic Functional Flow of the SPE Mapper Transmit Section........................................................................196 Basic Functional Flow Of The SPE Mapper Receive to AU-3/STS-1 SPE Mapping (Used in North American to TUG-3 Mapping (Used in ITU/ETSI standard based to AU-3/STS-1 SPE Mapping (Used in Telcordia*/ANSI Standards Based to TUG-3 Mapping (Used in ITU/ETSI Standard Based Systems)........................................................199 SPE Mapper Basic DS3 Configuration.........................................................................................................................................200 Phase Detector for External DS3 PLL...........................................................................................................201 Serial STS-1 SPE Channel (NSMI)...............................................................................................................201 TMUX Interface to the SPE Mapper..............................................................................................................202 PATH Termination Block...............................................................................................................................203 SPE Mapper Receive Direction Requirements..............................................................................................207 Transmit Direction (to SONET/SDH Line).....................................................................................................217 POAC Insert...................................................................................................................................................220 AIS Path Generation......................................................................................................................................221 SPE Mapper Register Descriptions...............................................................................................................222 SPE Mapper Register Map............................................................................................................................242 VT/TU Mapper Functional Description.................................................................................................................246 VT/TU Mapper Introduction...........................................................................................................................246 VT/TU Mapper Features................................................................................................................................246 VT/TU Mapper Functional Block Diagram.....................................................................................................247 VT/TU Mappings............................................................................................................................................249 VT/TU Locations............................................................................................................................................250 VT/TU Mapper Receive Path Description......................................................................................................252 VT Demultiplexer (VTDEMUX)......................................................................................................................252 VT Pointer Interpreter (VTPI).........................................................................................................................252 VT Termination (VTTERM)............................................................................................................................256 J2 Byte Monitor and Termination (J2MON)...................................................................................................260 Receive Signaling (RX_VTSIG).....................................................................................................................261 Receive Lower-Order Path Overhead (RX_LOPOH)....................................................................................262 Lucent Technologies Inc. 3