TIBPAL16L8/R4/6/8-10C, -12M by Texas Instruments Datasheet | DigiKey

TIBPAL16L8/R4/6/8-10C, -12M Datasheet by Texas Instruments

max (w/o feedback) TIBPAL16H’-10C S TIBPAL16H’-12M max (with feedback) [ U ] TIBPAL16H’-10C i: ] TIBPAL16H’-12M i: ] Propagation Delay I [ ] TIBPAL16L’-10C Series. . . 10 ns Max I 4 ‘7 TIBPAL16L’-12M Series... 12 ns Max 'i g 12% 0 Functionally Equivalent, but Faster than, I [ 7 14] Existing 20-Pin PLDs |[ a is] 0 Preload Capability on Output Registers (EMF 9 ‘2] Simplifies Testing E m H J 0 Power-Up Clear on Registered Devices (All Register Outputs are Set Low, but Voltage Levels at the Output Pins Go High) 0 Package Options Include Both Plastic and Ceramic Chip Carriers in Addition to Plastic and Ceramic DlPs 0 Security Fuse Prevents Duplication 0 Dependable Texas Instruments Quality and E Reliability i: I 3—STATE REGISTERED ”0 i: 59"“ INPUTS o OUTPUTS o ourrurs P05“ E PALlGLB 10 2 0 6 PALTEFM E 0 4 (Estate butters) A PALTEFKE E 0 6 (Estate butters) 2 PALTEFKB E 0 5 (Estate butters) 0 description Pin assignments in oper These programmable array logic devices feature high speed and functional equivalency w currently available devices. These lMPACT-X'M circuits combine the latest Advanced L technology with proven titanium-tungsten fuses to provide reliable, hign-performa conventional TTL logic. Their easy programmability allows for quick design of custom fu results in a more compact circuit board. In addition, chip carriers are available for futh space. All of the register outputs are set to a low level during power up. Extra circuitry has been pro of each register asynchronously to either a high or low state. This feature simplifies testing can be set to an initial state prior to executing the test sequence. The TIBPAL16' C series is characterized from 0°C to 75CC. The TIBPAL16' M serie operation over the full military temperature range of —55CC to 125°C. lMPACTrX is atrademark of Texas instruments Incorporated, PAL is a registered trademark of Advanced Micro Devices Inc. wonucnau w W”... "alum m. We, Prelim:cnnlarmlgurtiliuliampermedlemixaflgnslns‘lmmfn‘rs w “PM” . 2” m .. mm. m "we" mm mm...“ m. ...imgai.l,...ii.im, ’ 9 ’ TEXAS POST ornca BOX 555m - DALMS TEXAS 75255
TIBPAL16L8-10C, TIBPAL16R4-10C, TIBPAL16R6-10C, TIBPAL16R8-10C
TIBPAL16L8-12M, TIBPAL16R4-12M, TIBPAL16R6-12M, TIBPAL16R8-12M
HIGH-PERFORMANCE IMPACT-X™PAL® CIRCUITS
SRPS017A − D3023, MAY 1987 − REVISED DECEMBER 2010
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright © 2010, Texas Instruments Incorporated
1
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
•High-Performance Operation:
fmax (w/o feedback)
TIBPAL16R’-10C Series . . . 62.5 MHz Min
TIBPAL16R’-12M Series . . . 56 MHz Min
fmax (with feedback)
TIBPAL16R’-10C Series . . . 55.5 MHz Min
TIBPAL16R’-12M Series . . . 48 MHz Min
Propagation Delay
TIBPAL16L’-10C Series . . . 10 ns Max
TIBPAL16L’-12M Series . . . 12 ns Max
•Functionally Equivalent, but Faster than,
Existing 20-Pin PLDs
•Preload Capability on Output Registers
Simplifies Testing
•Power-Up Clear on Registered Devices (All
Register Outputs are Set Low, but Voltage
Levels at the Output Pins Go High)
•Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
•Security Fuse Prevents Duplication
•Dependable Texas Instruments Quality and
Reliability
DEVICE I
INPUTS
3-STATE
O OUTPUTS
REGISTERED
Q OUTPUTS
I/O
PORT
S
PAL16L8 10 2 0 6
PAL16R4 8 0 4 (3-state buffers) 4
PAL16R6 8 0 6 (3-state buffers) 2
PAL16R8 8 0 8 (3-state buffers) 0
description
These programmable array logic devices feature high speed and functional equivalency when compared with
currently available devices. These IMPACT-X™ circuits combine the latest Advanced Low-Power Schottky
technology with proven titanium-tungsten fuses to provide reliable, high-performance substitutes for
conventional TTL logic. Their easy programmability allows for quick design of custom functions and typically
results in a more compact circuit board. In addition, chip carriers are available for futher reduction in board
space.
All of the register outputs are set to a low level during power up. Extra circuitry has been provided to allow loading
of each register asynchronously to either a high or low state. This feature simplifies testing because the registers
can be set to an initial state prior to executing the test sequence.
The TIBPAL16’ C series is characterized from 0°C to 75°C. The TIBPAL16’ M series is characterized for
operation over the full military temperature range of −55°C to 125°C.
IMPACT-X is a trademark of Texas Instruments Incorporated.
PAL is a registered trademark of Advanced Micro Devices Inc.
Pin assignments in operating mode
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
I
I
I
I
I
I
I
I
I
GND
VCC
O
I/O
I/O
I/O
I/O
I/O
I/O
O
I
TIBPAL16L8’
C SUFFIX . . . J OR N PACKAGE
M SUFFIX . . . J PACKAGE
(TOP VIEW)
3 2 1 20 19
910111213
4
5
6
7
8
18
17
16
15
14
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
TIBPAL16L8’
C SUFFIX . . . FN PACKAGE
M SUFFIX . . . FK PACKAGE
(TOP VIEW)
I
I
I
O
I/O O
I
GND
I
VCC
_|:|:|:|:L O> MO _L_|:|:|:L O> MO _|:|:L_|:L lg” Pm assugnments m oper TEXAS {9 S’TRUMENTS IN
TIBPAL16R4-10C, TIBPAL16R6-10C, TIBPAL16R8-10C
TIBPAL16R4-12M, TIBPAL16R6-12M, TIBPAL16R8-12M
HIGH-PERFORMANCE IMPACT-X™PAL® CIRCUITS
SRPS017A − D3023, MAY 1987 − REVISED DECEMBER 2010
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2
Pin assignments in operating mode
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
CLK
I
I
I
I
I
I
I
I
GND
VCC
I/O
I/O
Q
Q
Q
Q
I/O
I/O
OE
(TOP VIEW)
TIBPAL16R4’
C SUFFIX . . . J OR N PACKAGE
M SUFFIX . . . J PACKAGE
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
CLK
I
I
I
I
I
I
I
I
GND
VCC
I/O
Q
Q
Q
Q
Q
Q
I/O
OE
(TOP VIEW)
TIBPAL16R6’
C SUFFIX . . . J OR N PACKAGE
M SUFFIX . . . J PACKAGE
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
CLK
I
I
I
I
I
I
I
I
GND
VCC
Q
Q
Q
Q
Q
Q
Q
Q
OE
(TOP VIEW)
TIBPAL16R8’
C SUFFIX . . . J OR N PACKAGE
M SUFFIX . . . J PACKAGE
I
I
CLK
I/O
I/O I/O
I
GND
VCC
OE
3 2 1 20 19
910111213
4
5
6
7
8
18
17
16
15
14
I/O
Q
Q
Q
Q
I
I
I
I
I
(TOP VIEW)
TIBPAL16R4’
C SUFFIX . . . FN PACKAGE
M SUFFIX . . . FK PACKAGE
I
I
CLK
I/O
QI/O
I
GND
VCC
3 2 1 20 19
910111213
4
5
6
7
8
18
17
16
15
14
Q
Q
Q
Q
Q
I
I
I
I
I
(TOP VIEW)
OE
TIBPAL16R6’
C SUFFIX . . . FN PACKAGE
M SUFFIX . . . FK PACKAGE
I
I
CLK
Q
QQ
I
GND
VCC
OE
3 2 1 20 19
910111213
4
5
6
7
8
18
17
16
15
14
Q
Q
Q
Q
Q
I
I
I
I
I
(TOP VIEW)
TIBPAL16R8’
C SUFFIX . . . FN PACKAGE
M SUFFIX . . . FK PACKAGE
TIBPALI GRA‘ r\, denoles lused Inputs TEXAS {9 INSTRUMENTS POST 0;;ch BOX 555303 - DALLAS TEXAS 75255
TIBPAL16L8-10C, TIBPAL16R4-10C
TIBPAL16L8-12M, TIBPAL16R4-12M
HIGH-PERFORMANCE IMPACT-X™PAL® CIRCUITS
SRPS017A − D3023, MAY 1987 − REVISED DECEMBER 2010
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3
functional block diagrams (positive logic)
denotes fused inputs
TIBPAL16L8’
TIBPAL16R4’
O
O
I/O
I/O
I/O
I/O
I/O
I/O
I
EN ≥1
&
32 X 64
10 16
166
7
7
7
7
7
7
7
7
6
16 x
Q
I/O
I/O
I/O
I/O
I
EN
816
164
7
7
7
8
8
8
7
4
16 x
≥1
&
32 X 64
≥1
8
Q
Q
Q
4
1D
I = 0 2
CLK C1
EN 2
OE
4
TIBPALI GRE‘ CLK 5/ « r\, denoles lused Inputs TEXAS {9 INSTRUMENTS 4 POST ancE BOX 555303 - DALLAS TEXAS 75235
TIBPAL16R6-10C, TIBPAL16R8-10C
TIBPAL16R6-12M, TIBPAL16R8-12M
HIGH-PERFORMANCE IMPACT-X™PAL® CIRCUITS
SRPS017A − D3023, MAY 1987 − REVISED DECEMBER 2010
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
4
functional block diagrams (positive logic)
denotes fused inputs
TIBPAL16R6’
TIBPAL16R8’
Q
I/O
I/O
I
EN
816
162
7
8
8
8
7
2
16 x
≥1
&
32 X 64
≥1
8
Q
Q
Q
6
1D
I = 0 2
CLK C1
EN 2
OE
6
8Q
8Q
Q
I816
168
8
8
8
8
16 x
8
Q
Q
Q
1D
I = 0 2
CLK C1
EN 2
8Q
8Q
&
32 X 64
≥1
OE
8Q
8Q
1 Flrst Fuse Numbers 15 u :2 so as 125 0 15a 192 m Increment I/O I/O I/O I/O I/O I/O 9 Fuse number 7 Flrsl vuse number + Increment TEXAS {9 INSTRUMENTS
0 4 8 12 16 20 24 28 31
I2
I3
I4
I5
I6
I7
I8
I9
O
19
I/O
18
I/O
17
I/O
16
I/O
15
I/O
14
I/O
13
O
12
I
11
Increment
I1
Fuse number = First fuse number + Increment
0
32
64
96
128
160
192
224
256
288
320
352
384
416
448
480
512
544
576
608
640
672
704
736
768
800
832
864
896
928
960
992
1024
1056
1088
1120
1152
1184
1216
1248
1280
1312
1344
1376
1408
1440
1472
1504
1536
1568
1600
1632
1664
1696
1728
1760
1792
1824
1856
1888
1920
1952
1984
2016
First
Fuse
Numbers
TIBPAL16L8-10C
TIBPAL16L8-12M
HIGH-PERFORMANCE IMPACT-X™PAL® CIRCUITS
SRPS017A − D3023, MAY 1987 − REVISED DECEMBER 2010
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5
logic diagram (positive logic)
CLK 4D Increment Flrst Fuse Numbers 0 4 a 12 Is 20 24 25 31 n a: 54 95 ms no “so ‘92 224 IIO IIO IIO Fuse number : First use number + Increment TEXAS {9 INSTRUMENTS
04812 16 20 24 28 31
I2
I3
I4
I5
I6
I7
I8
I9
I/O
19
I/O
18
Q
17
Q
16
Q
15
Q
14
I/O
13
I/O
12
11
Increment
CLK 1
Fuse number = First fuse number + Increment
0
32
64
96
128
160
192
224
256
288
320
352
384
416
448
480
512
544
576
608
640
672
704
736
768
800
832
864
896
928
960
992
1024
1056
1088
1120
1152
1184
1216
1248
1280
1312
1344
1376
1408
1440
1472
1504
1536
1568
1600
1632
1664
1696
1728
1760
1792
1824
1856
1888
1920
1952
1984
2016
First
Fuse
Numbers
C1
1D
I = 0
C1
1D
I = 0
C1
1D
I = 0
C1
1D
I = 0
OE
TIBPAL16R4-10C
TIBPAL16R4-12M
HIGH-PERFORMANCE IMPACT-X™PAL® CIRCUITS
SRPS017A − D3023, MAY 1987 − REVISED DECEMBER 2010
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
6
logic diagram (positive logic)
1 CLK Flrst Fuse Numbers 1) a: an 95 125 151) 192 224 Increment /\ 15 TEXAS {9 INSTRUMENTS 19 1a 17 16 15 14 13 IIO
0 4 8 12 16 20 24 28 31
I2
I3
I4
I5
I6
I7
I8
I9
I/O
19
Q
17
Q
16
Q
15
Q
14
I/O
12
11
Increment
CLK 1
Fuse number = First fuse number + Increment
0
32
64
96
128
160
192
224
256
288
320
352
384
416
448
480
512
544
576
608
640
672
704
736
768
800
832
864
896
928
960
992
1024
1056
1088
1120
1152
1184
1216
1248
1280
1312
1344
1376
1408
1440
1472
1504
1536
1568
1600
1632
1664
1696
1728
1760
1792
1824
1856
1888
1920
1952
1984
2016
First
Fuse
Numbers
C1
1D
I = 0
C1
1D
I = 0
C1
1D
I = 0
C1
1D
I = 0
OE
Q
18
C1
1D
I = 0
Q
13
C1
1D
I = 0
TIBPAL16R6-10C
TIBPAL16R6-12M
HIGH-PERFORMANCE IMPACT-X™PAL® CIRCUITS
SRPS017A − D3023, MAY 1987 − REVISED DECEMBER 2010
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7
logic diagram (positive logic)
1 CLK Flrst Fuse Numbers 1) a: an as 125 151) 192 2 224 Increment 1s Fuse number : First use number + Increment TEXAS {9 INSTRUMENTS 19 1a 17 16 15 14 13 12 11
0 4 8 12 16 20 24 28 31
I2
I3
I4
I5
I6
I7
I8
I9
Q
17
Q
16
Q
15
Q
14
11
Increment
CLK 1
Fuse number = First fuse number + Increment
0
32
64
96
128
160
192
224
256
288
320
352
384
416
448
480
512
544
576
608
640
672
704
736
768
800
832
864
896
928
960
992
1024
1056
1088
1120
1152
1184
1216
1248
1280
1312
1344
1376
1408
1440
1472
1504
1536
1568
1600
1632
1664
1696
1728
1760
1792
1824
1856
1888
1920
1952
1984
2016
First
Fuse
Numbers
C1
1D
I = 0
C1
1D
I = 0
C1
1D
I = 0
C1
1D
I = 0
OE
Q
18
C1
1D
I = 0
Q
13
C1
1D
I = 0
Q
19
C1
1D
I = 0
Q
12
C1
1D
I = 0
TIBPAL16R8-10C
TIBPAL16R8-12M
HIGH-PERFORMANCE IMPACT-X™PAL® CIRCUITS
SRPS017A − D3023, MAY 1987 − REVISED DECEMBER 2010
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
8
logic diagram (positive logic)
TEXAS *9 INSTRUMENTS
TIBPAL16L8-10C, TIBPAL16R4-10C, TIBPAL16R6-10C, TIBPAL16R8-10C
HIGH-PERFORMANCE IMPACT-X™PAL® CIRCUITS
SRPS017A − D3023, MAY 1987 − REVISED DECEMBER 2010
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage (see Note 1) 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage applied to disabled output (see Note 1) 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range 0°C to 75°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NOTE 1: These ratings apply except for programming pins during a programming cycle.
recommended operating conditions
MIN NOM MAX UNIT
VCC Supply voltage 4.75 5 5.25 V
VIH High-level input voltage (see Note 2) 2 5.5 V
VIL Low-level input voltage (see Note 2) 0.8 V
IOH High-level output current −3.2 mA
IOL Low-level output current 24 mA
fclock Clock frequency 0 62.5 MHz
High 8
Low 8
tsu Setup time, input or feedback before clock↑10 ns
thHold time, input or feedback after clock↑0 ns
TAOperating free-air temperature 0 25 75 °C
NOTE 2: These are absolute voltage levels with respect to the ground pin of the device and include all overshoots due to system and/or tester
noise. Testing these parameters should not be attempted without suitable equipment.
electrical characteristics over recommended operating free-air temperature range
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
VIK VCC = 4.75 V, II = −18 mA −0.8 −1.5 V
VOH VCC = 4.75 V, IOH = −3.2 mA 2.4 3.2 V
VOL VCC = 4.75 V, IOL = 24 mA 0.3 0.5 V
IOZH‡VCC = 5.25 V, VO = 2.4 V 100 μA
IOZL‡VCC = 5.25 V, VO = 0.4 V −100 μA
IIVCC = 5.25 V, VI = 5.5 V 0.2 mA
IIH‡VCC = 5.25 V, VI = 2.4 V 25 μA
IIL‡VCC = 5.25 V, VI = 0.4 V −0.08 −0.25 mA
IOS§VCC = 5.25 V, VO = 0 −30 −70 −130 mA
ICC VCC = 5.25 V, VI = 0, Outputs open 140 180 mA
Cif = 1 MHz, VI = 2 V 5 pF
Cof = 1 MHz, VO = 2 V 6 pF
Ci/o f = 1 MHz, VI/O = 2 V 7.5 pF
Cclk f = 1 MHz, VCLK = 2 V 6 pF
†All typical values are at VCC = 5 V, TA = 25°C.
‡I/O leakage is the worst case of IOZL and IIL or IOZH and IIH respectively.
§Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
ns
Pulse duration, clock (see Note 2)
tw
I ‘ mm TEXAS {9 INSTRUMENTS
fmax MHz
TIBPAL16L8-10C, TIBPAL16R4-10C, TIBPAL16R6-10C, TIBPAL16R8-10C
HIGH-PERFORMANCE IMPACT-X™PAL® CIRCUITS
SRPS017A − D3023, MAY 1987 − REVISED DECEMBER 2010
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
10
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER FROM
(INPUT)
TO
(OUTPUT) TEST CONDITION MIN TYP†MAX UNIT
With feedback 55.5 80
Without feedback 62.5 85
tpd I, I/O O, I/O R1 = 200 Ω, 3 7 10 ns
tpd CLK↑QR2 = 390 Ω, 2 5 8 ns
ten OE↓QSee Figure 3 1 4 10 ns
tdis OE↑Q 1 4 10 ns
ten I, I/O O, I/O 3 8 10 ns
tdis I, I/O O, I/O 3 8 10 ns
†All typical values are at VCC = 5 V, TA = 25°C.
‡fmax(with feedback) +1
tsu )tpd (CLK to Q)
, fmax(without feedback) +1
twhigh )twlow
TEXAS *9 INSTRUMENTS
TIBPAL16L8-12M, TIBPAL16R4-12M, TIBPAL16R6-12M, TIBPAL16R8-12M
HIGH-PERFORMANCE IMPACT-X™PAL® CIRCUITS
SRPS017D − D3023, MAY 1987 − REVISED DECEMBER 2010
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage (see Note 1) 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage applied to disabled output (see Note 1) 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range −55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NOTE 1: These ratings apply except for programming pins during a programming cycle.
recommended operating conditions
MIN NOM MAX UNIT
VCC Supply voltage 4.5 5 5.5 V
VIH High-level input voltage 2 5.5 V
VIL Low-level input voltage 0.8 V
IOH High-level output current −2 mA
IOL Low-level output current 12 mA
fclock†Clock frequency 0 56 MHz
High 9
Low 9
tsu†Setup time, input or feedback before clock↑11 ns
th†Hold time, input or feedback after clock↑0 ns
TAOperating free-air temperature −55 25 125 °C
NOTE 2: These are absolute voltage levels with respect to the ground pin of the device and include all overshoots due to system and/or tester
noise. Testing these parameters should not be attempted without suitable equipment.
electrical characteristics over recommended operating free-air temperature range
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
VIK VCC = 4.5 V, II = −18 mA −0.8 −1.5 V
VOH VCC = 4.5 V, IOH = −2 mA 2.4 3.2 V
VOL VCC = 4.5 V, IOL = 12 mA 0.3 0.5 V
IOZH‡VCC = 5.5 V, VO = 2.4 V 100 μA
IOZL‡VCC = 5.5 V, VO = 0.4 V −100 μA
IIVCC = 5.5 V, VI = 5.5 V 0.2 mA
IIH‡VCC = 5.5 V, VI = 2.4 V 25 μA
IIL‡VCC = 5.5 V, VI = 0.4 V −0.08 −0.25 mA
IOS§VCC = 5.5 V, VO = 0.5 V −30 −70 −250 mA
ICC VCC = 5.5 V, VI = GND, Outputs open 140 220 mA
Cif = 1 MHz, VI = 2 V 5 pF
Cof = 1 MHz, VO = 2 V 6 pF
Ci/o f = 1 MHz, VI/O = 2 V 7.5 pF
Cclk f = 1 MHz, VCLK = 2 V 6 pF
†All typical values are at VCC = 5 V, TA = 25°C.
‡I/O leakage is the worst case of IOZL and IIL or IOZH and IIH respectively.
§Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. VO is set at 0.5 V to
avoid test problems caused by test equipment ground degradation.
ns
Pulse duration, clock (see Note 2)tw
I ‘ mm TEXAS {9 INSTRUMENTS
fmax MHz
TIBPAL16L8-12M, TIBPAL16R4-12M, TIBPAL16R6-12M, TIBPAL16R8-12M
HIGH-PERFORMANCE IMPACT-X™PAL® CIRCUITS
SRPS017D − D3023, MAY 1987 − REVISED DECEMBER 2010
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
12
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER FROM
(INPUT)
TO
(OUTPUT) TEST CONDITION MIN TYP†MAX UNIT
With feedback 48 80
Without feedback 56 85
tpd I, I/O O, I/O R1 = 390 Ω, 3 7 12 ns
tpd CLK↑QR2 = 750 Ω, 2 5 10 ns
ten OE↓QSee Figure 3 1 4 10 ns
tdis OE↑Q 1 4 10 ns
ten I, I/O O, I/O 3 8 14 ns
tdis I, I/O O, I/O 2 8 12 ns
†All typical values are at VCC = 5 V, TA = 25°C.
‡fmax(with feedback) +1
tsu )tpd (CLK to Q)
, fmax(without feedback) +1
twhigh )twlow
TEXAS {9 S’TRUMENTS IN
TIBPAL16L8-10C, TIBPAL16R4-10C, TIBPAL16R6-10C, TIBPAL16R8-10C
TIBPAL16L8-12M, TIBPAL16R4-12M, TIBPAL16R6-12M, TIBPAL16R8-12M
HIGH-PERFORMANCE IMPACT-X™PAL® CIRCUITS
SRPS017A − D3023, MAY 1987 − REVISED DECEMBER 2010
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13
programming information
Texas Instruments programmable logic devices can be programmed using widely available software and
inexpensive device programmers.
Complete programming specifications, algorithms, and the latest information on hardware, software, and
firmware are available upon request. Information on programmers capable of programming Texas Instruments
programmable logic is also available, upon request, from the nearest TI field sales office, local authorized TI
distributor, or by calling Texas Instruments at (214) 997-5666.
preload procedure for registered outputs (see Figure 1 and Note 3)
The output registers can be preloaded to any desired state during device testing. This permits any state to be
tested without having to step through the entire state-machine sequence. Each register is preloaded individually
by following the steps given below.
Step 1. With VCC at 5 volts and Pin 1 at VIL, raise Pin 11 to VIHH.
Step 2. Apply either VIL or VIH to the output corresponding to the register to be preloaded.
Step 3. Pulse Pin 1, clocking in preload data.
Step 4. Remove output voltage, then lower Pin 11 to VIL. Preload can be verified by observing the
voltage level at the output pin.
td
tsu
tw
td
VIHH
VIL
VIL
VOL
VOH
VIH
Pin 11
Pin 1
Registered I/O Input Output
VIH
VIL
Figure 1. Preload Waveforms
NOTE 3: td = tsu = th = 100 ns to 1000 ns VIHH = 10.25 V to 10.75 v
TEXAS {9 S’TRUMENTS IN
TIBPAL16L8-10C, TIBPAL16R4-10C, TIBPAL16R6-10C, TIBPAL16R8-10C
TIBPAL16L8-12M, TIBPAL16R4-12M, TIBPAL16R6-12M, TIBPAL16R8-12M
HIGH-PERFORMANCE IMPACT-X™PAL® CIRCUITS
SRPS017A − D3023, MAY 1987 − REVISED DECEMBER
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
14
power-up reset (see Figure 2)
Following power up, all registers are reset to zero. This feature provides extra flexibility to the system designer
and is especially valuable in simplifying state-machine initialization. To ensure a valid power-up reset, it is
important that the rise of VCC be monotonic. Following power-up reset, a low-to-high clock transition must not
occur until all applicable input and feedback setup times are met.
1.5 V
tsu‡
tpd†
tw
VIL
VIH
5 V
VCC
Active Low
Registered Output
CLK
4 V
VOH
VOL
1.5 V
(600 ns TYP, 1000 ns MAX)
1.5 V
†This is the power-up reset time and applies to registered outputs only. The values shown are from characterization data.
‡This is the setup time for input or feedback.
Figure 2. Power-Up Reset Waveforms
\ —H—H “—‘f 4‘ {t +1 \+ ‘ \ ‘ ,7, ‘ iiiL‘, ‘ x 1; ‘ ‘E,,i n—p‘P % w y TEXAS {9 INSTRUMENTS POST OFFICE BOX 555303 - DALLAS IEXAS 75255
TIBPAL16L8-10C, TIBPAL16R4-10C, TIBPAL16R6-10C, TIBPAL16R8-10C
TIBPAL16L8-12M, TIBPAL16R4-12M, TIBPAL16R6-12M, TIBPAL16R8-12M
HIGH-PERFORMANCE IMPACT-X™PAL® CIRCUITS
SRPS017A − D3023, MAY 1987 − REVISED DECEMBER 2010
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15
PARAMETER MEASUREMENT INFORMATION
tsu
S1
R2
CL
(see Note A)
LOAD CIRCUIT FOR
3-STATE OUTPUTS
(3.5 V) [3 V]
(0.3 V) [0]
1.5 V
1.5 V
th
1.5 V
tpd
tpd
tpd
tpd
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOH
VOH
VOL
VOL
1.5 V 1.5 V
1.5 V 1.5 V
tw
1.5 V 1.5 V
≈ 3.3 V
VOL
VOH
VOH −0.5 V
≈ 0 V
ten
ten
tdis
tdis
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATIONS
1.5 V 1.5 V
1.5 V
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V
R1
VOL +0.5 V
5 V
(3.5 V) [3 V]
(0.3 V) [0]
(3.5 V) [3 V]
(0.3 V) [0]
(3.5 V) [3 V]
(0.3 V) [0]
(3.5 V) [3 V]
(0.3 V) [0]
(3.5 V) [3 V]
(0.3 V) [0]
From Output
Under Test
Test
Point
Input
Out-of-Phase
Output
(see Note D)
Timing
Input
Data
Input
In-Phase
Output
High-Level
Pulse
Low-Level
Pulse
Output
Control
(low-level
enabling)
Waveform 1
S1 Closed
(see Note B)
Waveform 2
S1 Open
(see Note B)
NOTES: A. CL includes probe and jig capacitance and is 50 pF for tpd and ten, 5 pF for tdis.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2
is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses have the following characteristics: For C suffix, use the voltage levels indicated in parentheses ( ), PRR ≤ 1 MHz,
tr = tf = 2 ns, duty cycle = 50%; For M suffix, use the voltage levels indicated in brackets [ ], PRR ≤ 10 MHz, tr and tf ≤ 2 ns, duty
cycle = 50%
D. When measuring propagation delay times of 3-state outputs, switch S1 is closed.
E. Equivalent loads may be used for testing.
Figure 3. Load Circuit and Voltage Waveforms
I'____'l | | i | (:1 | | | | | | —.7 I : ‘D | | f m L_____l \_—— N Fallures TEXAS {9 INSTRUMENTS 15 POST omcE BOX 55530: - DALLAS TEXAS 75255
TIBPAL16R4-10C, TIBPAL16R6-10C, TIBPAL16R8-10C
HIGH-PERFORMANCE IMPACT-X™PAL® CIRCUITS
SRPS017 − D3023, MAY 1987 − REVISED DECEMBER 2010
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
16
metastable characteristics of TIBPAL16R4-10C, TIBPAL16R6-10C, and TIBPAL16R8-10C
At some point a system designer is faced with the problem of synchronizing two digital signals operating at two
different frequencies. This problem is typically overcome by synchronizing one of the signals to the local clock
through use of a flip-flop. However, this solution presents an awkward dilemma since the setup and hold time
specifications associated with the flip-flop are sure to be violated. The metastable characteristics of the flip-flop
can influence overall system reliability.
Whenever the setup and hold times of a flip-flop are violated, its output response becomes uncertain and is said
to be in the metastable state if the output hangs up in the region between VIL and VIH. This metastable condition
lasts until the flip-flop falls into one of its two stable states, which takes longer than the specified maximum
propagation delay time (CLK to Q max).
From a system engineering standpoint, a designer cannot use the specified data sheet maximum for
propagation delay time when using the flip-flop as a data synchronizer − how long to wait after the specified data
sheet maximum must be known before using the data in order to guarantee reliable system operation.
The circuit shown in Figure 4 can be used to evaluate MTBF (Mean Time Between Failure) and Δt for a selected
flip-flop. Whenever the Q output of the DUT is between 0.8 V and 2 V, the comparators are in opposite states.
When the Q output of the DUT is higher than 2 V or lower than 0.8 V, the comparators are at the same logic level.
The outputs of the two comparators are sampled a selected time (Δt) after SCLK. The exclusive OR gate detects
the occurrence of a failure and increments the failure counter.
C1
C1 +
1D
1D
C1
C1
1D
VIH
Comparator
VIL
Comparator
Noise
Generator
DUT
MTBF
Counter
1D
DATA IN
SCLK
SCLK + Δt
Figure 4. Metastable Evaluation Test Circuit
In order to maximize the possibility of forcing the DUT into a metastable state, the input data signal is applied
so that it always violates the setup and hold time. This condition is illustrated in the timing diagram in Figure 5.
Any other relationship of SCLK to data will provide less chance for the device to enter into the metastable state.
Δt
Δt
SCLK + Δt
trec = Δt − CLK to Q (max)
MTBF +Time (sec)
# Failures
Data
SCLK
Figure 5. Timing Diagram
MTBF MTBF TEXAS {9 INSTRUMENTS
TIBPAL16R4-10C, TIBPAL16R6-10C, TIBPAL16R8-10C
HIGH-PERFORMANCE IMPACT-X™PAL® CIRCUITS
SRPS017A − D3023, MAY 1987 − REVISED DECEMBER 2010
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17
By using the described test circuit, MTBF can be determined for several different values of Δt (see Figure 4).
Plotting this information on semilog scale demonstrates the metastable characteristics of the selected flip-flop.
Figure 6 shows the results for the TIBPAL16’-10C operating at 1 MHz.
0 10203040506070
MTBF (s)
10 1
10 2
10 3
10 4
10 5
10 6
10 7
10 8
10 9
Δt (ns)
fclk = 1 MHz
fdata = 500 kHz
10 yr
1 yr
1 mo
1 day
1 wk
1 hr
1 min
10 s
Figure 6. Metastable Characteristics
From the data taken in the above experiment, an equation can be derived for the metastable characteristics at
other clock frequencies.
The metastable equation: 1
MTBF +fSCLK xf
data xC1e(*C2 x Dt)
The constants C1 and C2 describe the metastable characteristics of the device. From the experimental data,
these constants can be solved for: C1 = 9.15 X 10−7 and C2 = 0.959
Therefore
1
MTBF +fSCLK xf
data x9.15x10
*7e(*0.959 x Dt)
definition of variables
DUT (Device Under Test): The DUT is a 10-ns registered PLD programmed with the equation Q : = D.
MTBF (Mean Time Between Failures): The average time (s) between metastable occurrences that cause a
violation of the device specifications.
fSCLK (system clock frequency): Actual clock frequency for the DUT.
fdata (data frequency): Actual data frequency for a specified input to the DUT.
C1: Calculated constant that defines the magnitude of the curve.
C2: Calculated constant that defines the slope of the curve.
trec (metastability recovery time): Minimum time required to guarantee recovery from metastability, at a given
MTBF failure rate. trec = Δt − tpd (CLK to Q, max)
Δt: The time difference (ns) from when the synchronizing flip-flop is clocked to when its output is sampled.
The test described above has shown the metastable characteristics of the TIBPAL16R4/R6/R8-10C series. For
additional information on metastable characteristics of Texas Instruments logic circuits, please refer to TI
Applications publication SDAA004, ”Metastable Characteristics, Design Considerations for ALS, AS, and LS
Circuits.’’
1 ompm Swltchlng if :m (I. wow 0. HO) «m (CLK m o) Fropagalion D \ ‘PHL ‘ \ cm (I. l/O m o, l/O) c 4|, no to c. we) , / \ \ / \ km {CLK m a) / / km 4cm m a) \ 3W ' I I . 5 l + ° \ I + $ I I I T «m (CLKto c» D I 2 3 4 Number av omp TEXASw INSTRUMENTS
TIBPAL16L8-10C, TIBPAL16R4-10C, TIBPAL16R6-10C, TIBPAL16R8-10C
TIBPAL16L8-12M, TIBPAL16R4-12M, TIBPAL16R6-12M, TIBPAL16R8-12M
HIGH-PERFORMANCE IMPACT-X™PAL® CIRCUITS
SRPS017A − D3023, MAY 1987 − REVISED DECEMBER 2010
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
18
TYPICAL CHARACTERISTICS
7
5
4
3
−75 −50 −25 0 25 50
Figure 7
Propagation Delay Time − ns
75 100 125
8
6
PROPAGATION DELAY TIME
vs
FREE- AIR TEMPERATURE
VCC = 5 V
CL = 50 pF
R1 = 200 Ω
R2 = 390 Ω
1 Output Switching
tPHL (I, I/O to O, I/O)
tPLH (I, I/O to O, I/O)
tPHL (CLK to Q)
tPLH (CLK to Q)
TA − Free- Air Temperature −°C
7
5
4
3
9
6
4.5 4.75 5 5.25 5.5
Figure 8
Propagation Delay Time − ns
8
PROPAGATION DELAY TIME
vs
SUPPLY VOLTAGE
VCC − Supply Voltage − V
tPLH (CLK to Q)
tPHL (CLK to Q)
tPHL (I, I/O to O, I/O)
tPLH (I, I/O to O, I/O)
TA = 25 °C
CL = 50 pF
R1 = 200 Ω
R2 = 390 Ω
7
5
4
3
012345
Figure 9
Propagation Delay Time − ns
9
10
11
678
8
6
PROPAGATION DELAY TIME
vs
NUMBER OF OUTPUTS SWITCHING
VCC = 5 V
TA = 25 °C
CL = 50 pF
R1 = 200 Ω
R2 = 390 Ω
Number of Outputs Switching
tPHL (I, I/O to O, I/O)
tPLH (I, I/O to O, I/O)
tPHL (CLK to Q)
tPLH (CLK to Q)
‘ vcc:5v TA:25‘C RI:ZODQ R2:JBDQ N. \\ \\\ // TEXAS {9 INSTRUMENTS
TIBPAL16L8-10C, TIBPAL16R4-10C, TIBPAL16R6-10C, TIBPAL16R8-10C
TIBPAL16L8-12M, TIBPAL16R4-12M, TIBPAL16R6-12M, TIBPAL16R8-12M
HIGH-PERFORMANCE IMPACT-X™PAL® CIRCUITS
SRPS017A − D3023, MAY 1987 − REVISED DECEMBER 2010
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19
TYPICAL CHARACTERISTICS
1 4 10 40 100
Figure 11
F − Frequency − MHz
POWER DISSIPATION
vs
FREQUENCY
8- BIT COUNTER MODE
800
600
900
700
VCC = 5 V
PD − Power Dissipation − mW
TA = 0 °C
TA = 25 °C
TA = 80 °C
130
120
110
100
−75 −50 −25 0 25 50
Figure 12
140
150
SUPPLY CURRENT
vs
FREE- AIR TEMPERATURE
180
75 100 125
TA − Free- Air Temperature −°C
ICC − Supply Current − mA
160
170 VCC = 5.5 V
VCC = 5.25 V
VCC = 5 V
VCC = 4.5 V
VCC = 4.75 V
CL − Load Capacitance − pF
10
6
4
2
100 200 300 400
Figure 10
Propagation Delay Time − ns
14
16
18
500
12
8
PROPAGATION DELAY TIME
vs
LOAD CAPACITANCE
VCC = 5 V
TA = 25 °C
R1 = 200 Ω
R2 = 390 Ω
1 Output Switching
tPHL (I, I/O to O, I/O)
tPLH (I, I/O to O, I/O)
tPHL (CLK to Q)
tPLH (CLK to Q)
0 600
Unprogrammed Device
{'1‘ TEXAS INSTRUMENTS
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SRPS017
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(314) 291-5350; Marshall (314) 291-4650.
NEW JERSEY: Anthem (201) 227-7960; Arrow/Schweber
(201) 227-7880, (609) 596-8000; Hall-Mark (201) 515-3000,
(609) 235-1900; Marshall (201) 882-0320, (609) 234-9100.
NEW MEXICO: Alliance (505) 292-3360.
NEW YORK: Long Island: Anthem (516) 864-6600;
Arrow/Schweber (516) 231-1000; Hall-Mark (516)
737-0600; Marshall (516) 273-2424; Zeus (914) 937-7400.
Rochester: Arrow/Schweber (716) 427-0300; Hall-Mark
(716) 425-3300; Marshall (716) 235-7620.
Syracuse: Marshall (607) 785-2345.
NORTH CAROLINA: Arrow/Schweber (919) 876-3132;
Hall-Mark (919) 872-0712; Marshall (919) 878-9882.
OHIO: Cleveland: Arrow/Schweber (216) 248-3990;
Hall-Mark (216) 349-4632; Marshall (216) 248-1788.
Columbus: Hall-Mark (614) 888-3313.
Dayton: Arrow/Schweber (513) 435-5563; Marshall (513)
898-4480; Zeus (513) 293-6162.
OKLAHOMA: Arrow/Schweber (918) 252-7537; Hall-Mark
(918) 254-6110.
OREGON: Almac/Arrow (503) 629-8090; Anthem (503)
643-1114; Marshall (503) 644-5050; Wyle (503) 643-7900.
PENNSYLVANIA: Anthem (215) 443-5150;
Arrow/Schweber (215) 928-1800; GRS (215) 922-7037;
(609) 964-8560; Marshall (412) 788-0441.
TEXAS: Austin: Arrow/Schweber (512) 835-4180;
Hall-Mark (512) 258-8848; Marshall (512) 837-1991; Wyle
(512) 345-8853;
Dallas: Anthem (214) 238-7100; Arrow/Schweber (214)
380-6464; Hall-Mark (214) 553-4300; Marshall (214)
233-5200; Wyle (214) 235-9953; Zeus (214) 783-7010;
Houston: Arrow/Schweber (713) 530-4700; Hall-Mark
(713) 781-6100; Marshall (713) 467-1666; Wyle (713)
879-9953.
UTAH: Anthem (801) 973-8555; Arrow/Schweber (801)
973-6913; Marshall (801) 973-2288; Wyle (801) 974-9953.
WASHINGTON: Almac/Arrow (206) 643-9992, Anthem
(206) 483-1700; Marshall (206) 486-5747; Wyle (206)
881-1150.
WISCONSIN: Arrow/Schweber (414) 792-0150; Hall-Mark
(414) 797-7844; Marshall (414) 797-8400.
CANADA: Calgary: Future (403) 235-5325;
Edmonton: Future (403) 438-2858;
Montreal: Arrow/Schweber (514) 421-7411; Future (514)
694-7710; Marshall (514) 694-8142
Ottawa: Arrow/Schweber (613) 226-6903; Future (613)
820-8313.
Quebec: Future (418) 897-6666.
Toronto: Arrow/Schweber (416) 670-7769;
Future (416) 612-9200; Marshall (416) 458-8046.
Vancouver: Arrow/Schweber (604) 421-2333;
Future (604) 294-1166.
l TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 21-Mar-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
5962-85155132A ACTIVE LCCC FK 20 1 TBD Call TI Call TI
5962-8515513RA ACTIVE CDIP J 20 1 TBD Call TI Call TI
5962-8515513SA ACTIVE CFP W 20 1 TBD Call TI Call TI
5962-85155142A OBSOLETE LCCC FK 20 TBD Call TI Call TI
5962-8515514RA OBSOLETE CDIP J 20 TBD Call TI Call TI
5962-8515514SA OBSOLETE CFP W 20 TBD Call TI Call TI
5962-85155152A ACTIVE LCCC FK 20 1 TBD Call TI Call TI
5962-8515515RA ACTIVE CDIP J 20 1 TBD Call TI Call TI
5962-8515515SA ACTIVE CFP W 20 1 TBD Call TI Call TI
5962-85155162A ACTIVE LCCC FK 20 1 TBD Call TI Call TI
5962-8515516RA ACTIVE CDIP J 20 1 TBD Call TI Call TI
5962-8515516SA ACTIVE CFP W 20 1 TBD Call TI Call TI
TIBPAL16L8-10CFN ACTIVE PLCC FN 20 46 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-245C-168 HR
TIBPAL16L8-10CN ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TIBPAL16L8-12MFKB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
TIBPAL16L8-12MJ ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type
TIBPAL16L8-12MJB ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type
TIBPAL16L8-12MWB ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type
TIBPAL16R4-10CFN NRND PLCC FN 20 46 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-245C-168 HR
TIBPAL16R4-10CN NRND PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TIBPAL16R4-12MFKB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
TIBPAL16R4-12MJ ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type
TIBPAL16R4-12MJB ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type
TIBPAL16R4-12MWB ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type
TIBPAL16R6-10CFN NRND PLCC FN 20 46 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-245C-168 HR
TIBPAL16R6-10CN NRND PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TIBPAL16R6-12MFKB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
l TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 21-Mar-2012
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TIBPAL16R6-12MJB ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type
TIBPAL16R6-12MWB ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type
TIBPAL16R8-10CFN OBSOLETE PLCC FN 20 TBD Call TI Call TI
TIBPAL16R8-10CN OBSOLETE PDIP N 20 TBD Call TI Call TI
TIBPAL16R8-12MFKB OBSOLETE LCCC FK 20 TBD Call TI Call TI
TIBPAL16R8-12MJ OBSOLETE CDIP J 20 TBD Call TI Call TI
TIBPAL16R8-12MJB OBSOLETE CDIP J 20 TBD Call TI Call TI
TIBPAL16R8-12MWB OBSOLETE CFP W 20 TBD Call TI Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
J (R76D1P7TM) CERAVVHC DUAL 1N7L1NE PACKAGE )4 LEADS SHOWN PWS u . W 14 e 18 20 0300 0300 0300 0300 E (7.52) (7.52) (7.62) (7.62) w 5 Est ass ass ass fl fl m m m m m E MAX 0.755 540 0.950 1.060 (19.94) (21.34) (24.35) (25.92) I ..15,,, 1 0 500 0,300 0,310 0.300 U U U U U U U C W (7.52) (7.52) (7.57) (7.52) 0.245 0.245 0.220 0.245 0.005 (1.65) 0 MW 0045 (1.14) (6.22) (6.22) (5.50) (6.22) 0000 ( . ) a «0005(0.13)MN m r ~ 0200 (5.05) MAX 7 ; Seatmg Pmne , 0 (3.30) MN 4 0 020 (0. 66) 0014 (0.36) 0715' 0100 (.)254 0.014 (0.36) 0,000 (0.20) 4040083/F 03/03 VOTES: A. AH Hneur d1mens1ons are 1’1 1mm (muhmeters) a, This druwmg '3 subject m change w'thout nnt'ce. 0, 1m package 15 hermehcoHy sewed mm a cemm 11a usmg q1ass mt. D. 11an pom 1’s prowded on cap fo' 1mm) 1den1111ca0an umy on press cemrmc 9055 m sea) 00W. E FaHs thin ML 513 1035 0011417114. 001141416. GDPPTTB 0'10 001017120
MECHANICAL DATA W (R—GDFP—FZO) CERAMIC DUAL FLATF’ACK Base urd Seahng P‘c've i 0009 (0‘23)? 0 mm (mm) o 320 (>353) MAX 4% 0 050 0540 (‘17?) MAX 0 005 (0,15) WN i 4 P‘cces n 370 ’94s) 6.250 (535) o 370 (9.40} 0 250 (6,35) 4040180 4/3 07/03 NUTS AH Mnec' mmens‘mrs 'e m mmes (whmems) TH: drawmq \s sums :0 change thruut mouse A B 0 TM: package can 35 wermsk'ctu sea‘ed m u ceram': Md usmq qmss H D E hdex pm ‘5 pruwded on cap 10> (erm'm‘ 'denhficufio" aw Fu‘a mum Vi‘iSid '535 cwzim INSrRUMEm-s www.1i.com
MECHANICAL DATA AME; CHEF“ ELAR‘REE ?< (a="" cm;="" w”)="" ,eamess="" c="" ’7="" flflflflflfl\="" f="" e="" e="" e="" e="" ,="" kwwwg="" qfijrm“="" a="" i:="" i7="" i4="" i:="" i:="" e7="" eiflfiiflfizj="" vvwwttflfl="" 1="" notes="" ah="" ineur="" dimensions="" are="" in="" inches="" (minmeiers).="" this="" cruwg="" i5="" subjeci="" i0="" chcnge="" without="" noiice="" this="" package="" car="" he="" hermeticuiiy="" secied="" mm="" a="" metai="" ic="" i'ciis="" wiihi="" jedec="" n87004="" 50m)="" {mm="" instruments="" w.="" (i.="" cam="">
MECHANICAL DATA N (R—PDlP-T“) PLASTIC DUAL—IN—LINE PACKAGE 16 P15 SHOWN PWS " A L . [NM 15 a 20 16 9 0 775 U 777 0 SZU '1 USE 3 , 1H HH HH r% r’H r"—1 r’H H1 1 A VAX “9‘69? (191591 (23,37) (25,92) 0 250 (6,50‘ A MN [1145‘ 0142‘ 0.350 new 3 O 240 (6.10), 15 92/ (1832/ (2 .59) (23,58) MSiUO‘ (A AA AA Ari AA AA AA R1 &. VAR1AT1CN M RR AC AD 1 B 0070( (17s) 0015 (111) A 0045 (1,111 g n > , ‘ -) 3.020 (0,51) MW w o 5 (0 35) 0200( 38) MAX f, ), Gnu E Home 1 1‘ 9 fix—1%)” 1 0125’ 1/111 4% 0010 (v.37 ) NOM 31a) U L»- J 0450 (13,92) MAX L 202‘ (0,53) » e c 015 (0,35) / \ a; 00‘s (0,Zb)® / \ 1 1 \\¥,// 11/18 Pm (My > @ 20 Pm vendor upho'v mom/r 17/7037 NO'FS A AH Mnec' mmensmr‘fi: B 1m: drawmq 1s sume m muss (m1111mevem) 0 change mm): nofice /c\ FuHs wumn JEDEC M57001, except 15 an: 20 p171 'r1111mLm body 1mm (01m A) A The 70 p171 and 15m} shmflder Md” 15 a ve'vdnr 0311071, eher NIH Dr 111 wkflh INSI'RUMENTS www.1i.com
1—11—11—11—11—1 1_l)_l)_l)_ll_l 0.000 10.20) NOM J L NO_ OF D/E Dl/E1 D2IE2 PINS " MIN MAX MIN MAX MIN MAX 20 0.3051978) 0,395110,03) 03501809) 035619104) 0.141 (3155) 0.1691429) 20 048511232) 049511257) 0450111143) 0.45611155) 0.1911405) 0.2191556) 44 058511140) 059511755) 055011551) 065511566) 0.2911739) 0.3191510) 52 078511994) 079512019) 075011905) 075611920) 0.3411066) 0.3691937) 50 098512502) 099512527) 095012413) 095012433) 044111120) 046911191) 54 115513010) 119513035) 115012921) 1.15012941) 054111074) 055911445) 4040005/ B 03/9 9051 OFFICE BOX 555303 - DALLAS TEXAS 75255
MECHANICAL DATA
MPLC004A – OCTOBER 1994
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FN (S-PQCC-J**) PLASTIC J-LEADED CHIP CARRIER
4040005/B 03/95
20 PIN SHOWN
0.026 (0,66)
0.032 (0,81)
D2/E2
0.020 (0,51) MIN
0.180 (4,57) MAX
0.120 (3,05)
0.090 (2,29)
D2/E2
0.013 (0,33)
0.021 (0,53)
Seating Plane
MAX
D2/E2
0.219 (5,56)
0.169 (4,29)
0.319 (8,10)
0.469 (11,91)
0.569 (14,45)
0.369 (9,37)
MAX
0.356 (9,04)
0.456 (11,58)
0.656 (16,66)
0.008 (0,20) NOM
1.158 (29,41)
0.958 (24,33)
0.756 (19,20)
0.191 (4,85)
0.141 (3,58)
MIN
0.441 (11,20)
0.541 (13,74)
0.291 (7,39)
0.341 (8,66)
18
19
14
13
D
D1
13
9
E1E
4
8
MINMAXMIN
PINS
**
20
28
44
0.385 (9,78)
0.485 (12,32)
0.685 (17,40)
52
68
84 1.185 (30,10)
0.985 (25,02)
0.785 (19,94)
D/E
0.395 (10,03)
0.495 (12,57)
1.195 (30,35)
0.995 (25,27)
0.695 (17,65)
0.795 (20,19)
NO. OF D1/E1
0.350 (8,89)
0.450 (11,43)
1.150 (29,21)
0.950 (24,13)
0.650 (16,51)
0.750 (19,05)
0.004 (0,10)
M
0.007 (0,18)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-018
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