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S80L186EB13 Datasheet(PDF) 42 Page - Intel Corporation |
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S80L186EB13 Datasheet(HTML) 42 Page - Intel Corporation |
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42 / 59 page  80C186EB80C188EB 80L186EB80L188EB RESET The processor will perform a reset operation any time the RESIN pin active The RESIN pin is actually synchronized before it is presented internally which means that the clock must be operating before a reset can take effect From a power-on state RESIN must be held active (low) in order to guarantee cor- rect initialization of the processor Failure to pro- vide RESIN while the device is powering up will result in unspecified operation of the device Figure 14 shows the correct reset sequence when first applying power to the processor An external clock connected to CLKIN must not exceed the VCC threshold being applied to the processor This is nor- mally not a problem if the clock driver is supplied with the same VCC that supplies the processor When attaching a crystal to the device RESIN must remain active until both VCC and CLKOUT are stable (the length of time is application specific and de- pends on the startup characteristics of the crystal circuit) The RESIN pin is designed to operate cor- rectly using an RC reset circuit but the designer must ensure that the ramp time for VCC is not so long that RESIN is never really sampled at a logic low level when VCC reaches minimum operating conditions Figure 16 shows the timing sequence when RESIN is applied after VCC is stable and the device has been operating Note that a reset will terminate all activity and return the processor to a known operat- ing state Any bus operation that is in progress at the time RESIN is asserted will terminate immediately (note that most control signals will be driven to their inactive state first before floating) While RESIN is active bus signals LOCK A19 ONCE and A1816 are configured as inputs and weakly held high by internal pullup transistors Only 19ONCE can be overdriven to a low and is used to enable ONCE Mode Forcing LOCK or A1816 low at any time while RESIN is low is prohibited and will cause unspecified device operation 42 42 |
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