Details, datasheet, quote on part number: PLL520-09
| Part | PLL520-09 |
| Category | Timing Circuits => Oscillators => VCXO (Voltage Controlled Crystal Oscillators) |
| Description | , 120-200MHz In, 120-800MHz Out, Pecl, Inverted oe |
| Company | PhaseLink (PLL) |
| Datasheet | Download PLL520-09 Datasheet |
| Features, Applications |
| Low Phase Noise VCXO with multipliers (for 120-200MHz Fund Xtal) FEATURES to 200MHz Fundamental Mode Crystal. Output range: � 200MHz (no multiplication), 400MHz (2x multiplier) 700MHz (4x multiplier). High yield design support to 2pF string capacitance at 200MHz. CMOS (Standard drive PLL520-07 or Selectoable Drive PLL520-06), PECL (Enable low PLL520-08 or Enable high PLL520-05) or LVDS output (PLL520-09). Integrated variable capacitors. Supports 3.3V-Power Supply. Available in 16-Pin (TSSOP or 3x3mm QFN) Note: PLL520-06 only available in 3x3mm. Note: PLL520-07 only available in TSSOP. PLL520-05/-06/-07/-08/-09 are VCXO IC specifically designed to pull high frequency fundamental crystals. Their design was optimized to tolerate higher limits of interelectrodes capacitance and bonding capacitance to improve yield. It achieves very low current into the crystal resulting in better overall stability. Its internal varicaps allow an on chip frequency pulling, controlled by the VCON input. SEL OE Vin X+ XOscillator Amplifier w/ integrated varicaps PLL (Phase Locked Loop)Internal pull-up PLL520-06 pin 12 is output drive select (DRIVSEL) (0 for High Drive CMOS, 1 for Standard Drive CMOS) OE 0 (Default) 0 1 (Default) State Output enabled Tri-state Output enabledOE input: Logical states defined by PECL levels for PLL520-08 Logical states defined by CMOS levels for PLL520-05/-06/-07/-09 Crystal in connector. Crystal out connector. Output enable pin.Description Frequency control input to 3.0V) GND (except pin on PLL520-06: DRIVSEL see below). PLL520-06 only: Drive Select Input. This pin has an internal pullup that will default DRIVSEL to `1' when not connect to GND. CMOS output of PLL520-06 will be high drive CMOS when DRIVSEL is set to `0', and will be standard CMOS otherwise. True output PECL (PLL520-08) or LVDS (PLL520-09) (N/C for PLL520-07) Complementary output PECL (PLL520-08) or LVDS (PLL520-09) (CMOS out for PLL520-07). P +3.3V VDD. Multiplier selector pins. These pins have an internal pull-up that will default SEL to `1' when not connected to GND. * Note: PLL520-06 only available in 3x3mm QFN, PLL520-07 only available in TSSOP. Note: DRIVSEL on pin on PLL520-06 only. Note: SEL3 is not available (always in 3x3mm package All pins have internal pull-ups (default value is 1). Connect to GND to set to 0. Supply Voltage Input Voltage, dc Output Voltage, dc Storage Temperature Ambient Operating Temperature* Junction Temperature Lead Temperature (soldering, 10s) Input Static Discharge Voltage Protection Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. * Note : Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for INDUSTRIAL grade only. Built-in Capacitance Inter-electrode capacitance C0/C1 ratio (gamma) Oscillation FrequencyVCXO Stabilization Time * VCXO Tuning Range CLK output pullability On-chip Varicaps control range Linearity VCXO Tuning Characteristic VCON input impedance VCON modulation BW 0V VCON -3dB 25 From power valid XTAL 300 0V VCON 3.3V, at room temp. VCON to 3.3VNote: Parameters denoted with an asterisk represent nominal characterization data and are not production tested to any specific limits. |
| Related products with the same datasheet |
| PLL520-06 |
| PLL520-07 |
| PLL520-08 |
| Some Part number from the same manufacture PhaseLink (PLL) |
| PLL520-10 , 65-130MHz In, 65-800MHz Out, CMOS,pecl,lvds |
| PLL520-17 , 65-130MHz In, 65-800MHz Out, CMOS |
| PLL520-20 , 120-200MHz In, 120-200MHz Out, Pecl,lvds |
| PLL520-28 , 120-200MHz In, 120-200MHz Out, Pecl |
| PLL520-30 , 65-130MHz In, 65-130MHz Out, Pecl,lvds |
| PLL520-38 , 65-130MHz In, 65-130MHz Out, Pecl |
| PLL520-40 , 65-130MHz In, 65-130MHz Out, CMOS |
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| PLL520-50 , 25-55MHz In, 12.5-55MHz Out, CMOS, +/- 190ppm Pull |
| PLL520-56 , 25-55MHz In, 25-55MHz Out, Hidrive CMOS |
| PLL520-57 , 25-55MHz In, 25-55MHz Out, Standard Drive CMOS |
| PLL520-70 , 45-90MHz In, 45-90MHz Out, CMOS |
| PLL520-77 |
| PLL600-10 , 10 - 52MHz In, 5 - 52MHz Out,CMOS, 2.25 - 3.63V |
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| PLL600-30 |
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| PLL601-01 , 1x to 16x Out, 10 - 27MHz In, -115dBc @ 1kHz |
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|
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