to 65MHz fundamental crystal input. Output range: � 65MHz Complementary outputs: PECL or LVDS output. Selectable OE Logic (enable high or enable low). Integrated variable capacitors. Supports or 3.3V Power Supply. Available in 16 pin TSSOP package.

The PLL520-88 (PECL) and PLL520-89 (LVDS) are VCXO ICs specifically designed to work with fundamental crystals between 19MHz and 65MHz. The selectable divide by two feature extends the operation range from to 65MHz. They require very low current into the crystal resulting in better overall stability. The OE logic feature allows selection of enable high or enable low.

Input selection: Bond to GND to set to "0", bond to VDD to set "1" No connection results to "default" setting through internal pull-up/-down. OE_CTRL: Logical states defined by PECL levels if OE_SELECT is "1" Logical states defined by CMOS levels if OE_SELECT is "0"

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 1

Name VDD XIN XOUT DNC S2 OE_CTRL VCON GND GNDBUF Q VDDBUF QBAR GNDBUF DNC Pin# Description Power Supply. Crystal input. See Crystal Specification on page 3. Crystal output. See Crystal Specification on page 3. Do Not Connect. Output Divide by Two selector pin. See the OUTPUT DIVIDE BY TWO SELECTOR Table on page 1. Output Enable input. See OUTPUT SELECTION AND ENABLE TABLE on page 1. Voltage control input. Ground. Ground for output buffer circuitry. PECL or LVDS output. Power supply for output buffer circuitry. Complementary PECL or LVDS output. Ground for output buffer circuitry. Do Not Connect. Do Not Connect.

Supply Voltage Input Voltage, dc Output Voltage, dc Storage Temperature Ambient Operating Temperature* Junction Temperature Lead Temperature (soldering, 10s) ESD Protection, Human Body Model

Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. * Note : Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 2

Note: Parameters denoted with an asterisk represent nominal characterization data and are not production tested to any specific limits.

VCXO Stabilization Time * VCXO Tuning Range CLK output pullability On-chip Varicaps control range Linearity VCXO Tuning Characteristic VCON input impedance VCON modulation BW

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 3