Selectable to 200MHz range. Low phase noise output 10kHz frequency offset, -140dBc/Hz for 17.664MHz, -132dBc/Hz for 35.328MHz, -125dBc/Hz for 155.52MHz). 4 CMOS outputs (in phase). to 25MHz crystal input. No external load capacitor or varicap required. Wide pull range (+/-190 ppm) Selectable to 8x frequency multiplier. 3.3V operation. Available in 14-SOP.

The PLL502-67 is high performance and low phase noise VCXO IC chip. It provides phase noise performance as low at 1kHz offset (at 17.664MHz) and at 1kHz offset 155.52MHz by multiplying the input crystal frequency to 8x. The wide pull range 190 ppm) and very low jitter makes this chip ideal for a wide range of applications, from xDSL to SONET/SDH and FEC. The chip accepts a low cost fundamental parallel resonant mode crystal from to 25MHz.

Frequency control input to 3.0V) GND. Output signal Output signal. Multiplier selector pins. These pins have an internal pull-up that will default SEL to `1' when not connected to GND. +3.3V VDD.

Supply Voltage Input Voltage, dc Output Voltage, dc Storage Temperature Ambient Operating Temperature* Junction Temperature Lead Temperature (soldering, 10s) Input Static Discharge Voltage Protection

Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. * Note : Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for INDUSTRIAL grade only.

Note : Crystal Loading rating: 9pF is the loading the crystal sees from the VCXO chip at VCON It is assumed that the crystal will be at nominal frequency at this load. If the crystal requires more load be at nominal frequency, the additional load must be added externally. This however may reduce the pull range.