VCXO output for the to 130MHz range to 130MHz Low phase noise (-142 dBc @ 10kHz offset). CMOS output with OE tri-state control. Selectable output drive (Standard or High drive). - Standard: 8mA drive capability at TTL level. - High: 24mA drive capability at TTL level. Fundamental crystal input. Integrated high linearity variable capacitors. 150 ppm pull range, max 5% linearity. Low jitter (RMS): 2.5ps period jitter. to 3.3V operation. Available in 8-Pin SOIC or DIE.

The PLL500-17B/27B/37B are a low cost, high performance, low phase noise, and high linearity VCXO family for the to 130MHz range, providing less than at 10kHz offset. The very low jitter (2.5 ps RMS period jitter) makes these chips ideal for applications requiring voltage controlled frequency sources. The IC's are designed to accept fundamental resonant mode crystals.

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Crystal input pin. Output Enable input pin. Disables the output when low. Internal pull-up enables output by default if pin is not connected low. Frequency control voltage input pin. Ground pin. Output clock pin. VDD power supply pin. Output drive select pin. High drive if set to `0'. Low drive if set to `1'. Internal pull-up. Crystal output pin. Ref clock input.

Supply Voltage Input Voltage, dc Output Voltage, dc Storage Temperature Ambient Operating Temperature* Junction Temperature Lead Temperature (soldering, 10s) ESD Protection, Human Body Model

Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. * Note : Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.

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VCXO Stabilization Time * VCXO Tuning Range CLK output pullability VCXO Tuning Characteristic Pull range linearity Power Supply Rejection VCON pin input impedance VCON modulation BW PWSRR

Note: Preliminary Specifications still to be characterized. Parameters denoted with an asterisk represent nominal characterization data and are not production tested to any specific limits.

RMS Period Jitter (1 sigma � 10,000 samples) Phase Noise relative to carrier Phase Noise relative to carrier Phase Noise relative to carrier Phase Noise relative to carrier Phase Noise relative to carrier

With capacitive decoupling between VDD and GND. @100Hz offset @1kHz offset @10kHz offset @100kHz offset @1MHz offset

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/21/05 Page 3