1 CPU Clock output with selectable frequencies or 133 MHz). 1 Selectable or 12MHz USB Clock output. Selectable Spread Spectrum (SST) for EMI reduction on CPU clock. PowerPC compatible CPU Clock. Advanced, low power, sub-micron CMOS processes. 14.31818MHz fundamental crystal input. 3.3V and/or 2.5V operation. Available 16-Pin 150mil SOP.

The is a low cost, low jitter, and high performance clock synthesizer for generic Printer applications. It provides one CPU clock and a selectable or 12MHz (USB) output. The user can choose among 9 different clock frequencies and 3-selectable downspread Spread Spectrum modulation to reduce EMI on CPU clock. All frequencies are generated from a single low cost 14.31818MHz crystal. CPU clock can be driven from an independent or 3.3V power supply.

Crystal input to be connected a 14.31818MHz fundamental crystal (CL = 20pF, parallel resonant mode). Load capacitors have been integrated on the chip. No external Load capacitor is required. Crystal Output 3.3V power supply and GND.

CPU and USB outputs have separate power supply pins (VDD and GND). VDDCPU can accept 3.3V and/or 2.5V power supply. Bi-directional pin. Upon power-on, the value of USB_SEL is latched in and used to select the USB output (see USB selection table below). After the input has been latched-in, the pin serves as USB or 12 MHz) output. 0=15k to GND, M=leave open, 1=15k to VDD_USB CPU clock signal output pin. The CPU clock frequency is selected as per the frequency table on page 1, depending on the value of FS(0:1). Bi-level input with internal Pull-up resistor for SST control (see Spread Spectrum selection table 0=connect to GND, 1=leave open (or to VDD). Tri-level inputs for CPU clock frequency selection (see table 0=connect to GND, M=not connected, 1=connect to VDDA.

In order to reduce pin usage, the PLL702-06 uses tri-level input pins. These pins allow 3 levels for input selection: namely, 0 = Connect to GND, 1 = Connect to VDD, = Do not connect. Thus, unlike the two-level selection pins, the tri-level input pins are in the "M" (mid) state when not connected. In order to connect a tri-level pin to a logical "zero", the pin must be connected to GND. Likewise, in order to connect to a logical "one", the pin must be connected to VDD.

NOTE: Rup=Internal pull-up resistor (see pin description). Power-up Reset : R starts from to 0 while RB starts from to 1.

The PLL702-06 also uses bi-directional pins. The same pin serves as input upon power-up, and as output as soon as the inputs have been latched. The value of the input is latched-in upon power-up. Depending on the pin (see pin description), the input can be tri-level or a standard two-level. Unlike unidirectional pins, bi-directional pins cannot be connected directly to GND or VDD in order to set the input or "1", since the pin also needs to serve as output. In the case of two level input pins, an internal pullup resistor is present. This allows a default value to be set when no external pull down resistor is connected between the pin and GND (by definition, a tri-level input has a default value of "M" (mid) it is not connected). In order to connect a bi-directional pin to a non-default value, the input must be connected to GND or VDD through an external pull-down/pull-up resistor.