Full CMOS, 6T Cell High Speed (Equal Access and Cycle Times) 10/12/15/20/25/35 ns (Commercial) 15/20/25/35 ns (Military) Low Power Operation 633/715 mW Active mW Active mW Standby (TTL Input) Output Enable Control Function Single 5V�10% Power Supply Common Data I/O Fully TTL Compatible Inputs and Outputs Produced with PACE II TechnologyTM Standard Pinout (JEDEC Approved) 24-Pin 300 mil DIP, SOIC, SOJ � 24-Pin Rectangular LCC x 400 mils) � 28-Pin Square LCC x 450 mils)

The a 16,384-bit ultra high-speed static RAMs organized x 8. The CMOS memories require no clocks or refreshing and have equal access and cycle times. Inputs are fully TTL-compatible. The RAMs operate from a single 5V�10% tolerance power supply. Current drain is typically 10 �A from a 2.0V supply. Access times as fast as 10 nanoseconds are available, permitting greatly enhanced system operating speeds. CMOS is used to reduce power consumption to a low 633 mW active, 193 mW standby. The P4C116 is available 24-pin 300 mil DIP, SOJ and SOIC packages providing excellent board level densities. The P4C116 is also available in 24-pin rectangular and 28-pin square LCC packages.

Symbol VCC Parameter Power Supply Pin with Respect to GND Terminal Voltage with Respect to GND (up to 7.0V) Operating Temperature Value �0.5 to VCC to +125 Unit V Symbol TBIAS TSTG �C PT IOUT Parameter Temperature Under Bias Storage Temperature Power Dissipation DC Output Current Value 1.0 50 Unit W mA

Over recommended operating temperature and supply voltage(2) P4C116 Symbol VIH VIL VHC VLC VCD VOL VOH ILI ILO ICC ISB ISBI Parameter Input High Voltage Input Low Voltage CMOS Input High Voltage CMOS Input Low Voltage Input Clamp Diode Voltage Output Low Voltage (TTL Load) Output High Voltage (TTL Load) Input Leakage Current Output Leakage Current Dynamic Operating Current 10, 12 Dynamic Operating Current 15, 20 Dynamic Operating Current 25, 35 Standby Power Supply Current (TTL Input Levels) VCC = Min., IIN �18 mA IOL = +8 mA, VCC = Min. IOH = �4 mA, VCC = Min. VCC = Max., VIN = GND to VCC = Max., CS = VIH, VOUT = GND to VCC = Max., f = Max., Outputs Open VCC = Max., f = Max., Outputs Open VCC = Max., f = Max., Outputs Open CE VIH, VCC = Max., f = Max., Outputs Open

Standby Power Supply CE VHC, VCC = Max., = 0, Outputs Open Current (CMOS Input Levels) VIN VLC or VIN VHC

Read Cycle Time Address Access Time Chip Enable Access Time Output Hold from Address Change Chip Enable to Output in Low Z Chip Disable to Output in High Z Output Enable Low to Data Valid Output Enable Low to Low Z Output Enable High to High Z Chip Enable to Power Up Time Chip Disable to Power Down

Notes: 1. Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to MAXIMUM rating conditions for extended periods may affect reliability. 2. Extended temperature operation guaranteed with 400 linear feet per minute of air flow. 3. Transient inputs with VIL and IIL not more negative than �3.0V and �100mA, respectively, are permissible for pulse widths to 20 ns.

4. This parameter is sampled and not 100% tested. WE is HIGH for READ cycle. CE is LOW and OE is LOW for READ cycle. 7. ADDRESS must be valid prior to, or coincident with CE transition LOW. 8. Transition is measured 200 mV from steady state voltage prior to change, with loading as specified in Figure 1. This parameter is sampled and not 100% tested. 9. Read Cycle Time is measured from the last valid address to the first transitioning address.