P4C1024L datasheet - Org = 128K X 8 ;; Features. = Common I/O, Low Power

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Details, datasheet, quote on part number: P4C1024L

Part	P4C1024L
Category	Memory => SRAM
Title	SRAM
Description	Org = 128K X 8 ;; Features. = Common I/O, Low Power ;; ;; Taa (ns) = 55 to 70 ;; Package / Pins Dip = 32 ;; Package / Pins Soj = . ;; Package / Pins Soic / Sop = 32
Company	Performance Semiconductor Corp.
Datasheet	Download P4C1024L Datasheet

Features, Applications

FEATURES

VCC Current (Commercial/Industrial) Operating: 70mA/85mA CMOS Standby: 100�A/100�A Access Times --55/70 (Commercial or Industrial) Single 5 Volts �10% Power Supply Easy Memory Expansion Using CE1, CE2 and OE Inputs Common Data I/O Three-State Outputs Fully TTL Compatible Inputs and Outputs Advanced CMOS Technology Automatic Power Down Packages --32-Pin 600 mil DIP --32-Pin 445 mil SOP

DESCRIPTION

The a 1,048,576-bit low power CMOS static RAM organized as 128Kx8. The CMOS memory requires no clocks or refreshing, and has equal access and cycle times. Inputs are fully TTL-compatible. The RAM operates from a single 5V�10% tolerance power supply. Access times 55 ns and 70 ns are availale. CMOS is utilized to reduce power consumption to a low level. The P4C1024L device provides asynchronous operation with matching access and cycle times. Memory locations are specified on address pins to A16. Reading is accomplished by device selection (CE1 low and CE2 high) and output enabling (OE) while write enable (WE) remains HIGH. By presenting the address under these conditions, the data in the addressed memory location is presented on the data input/output pins. The input/output pins stay in the HIGH Z state when either OE is HIGH CE2 is LOW. The P4C1024L is packaged 32-pin 445 mil SOP as well a 600 mil PDIP.

Temperature Range (Ambient) Commercial to 70�C) Industrial to 85�C) Supply Voltage 4.5V VCC 5.5V 4.5 VCC 5.5V

Stresses greater than those listed can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of this data sheet. Exposure to Maximum Ratings for extended periods can adversely affect device reliability. Symbol VCC VTERM TA STG IOUT ILAT Parameter Supply Voltage with Respect to GND Terminal Voltage with Respect to GND (up to 7.0V) Operating Ambient Temperature Storage Temperature Output Current into Low Outputs Latch-up Current >200 Min Max 7.0 VCC Unit �C mA

(Over Recommended Operating Temperature & Supply Voltage) Symbol VOH VOL VIH VIL ILI ILO ISB Parameter Output High Voltage - I/O7) Output Low Voltage - I/O7) Input High Voltage Input Low Voltage Input Leakage Current Output Leakage Current VCC Current TTL Standby Current (TTL Input Levels) VCC Current CMOS Standby Current (CMOS Input Levels) GND VIN VCC GND VOUT VCC CE1 VIH or CE2 VIL VCC = 5.5V, IOUT CE1 = VIH CE2 = VIL VCC = 5.5V, IOUT mA CE1 VCC CE2 0.2V Ind'l. Com'l. Ind'l. Com'l. Test Conditions IOH = �1mA, VCC = 4.5V IOL = 2.1mA Min 2.4 0.4 VCC Max Unit �A mA

(VCC = 1.0 MHz) Symbol CIN COUT Parameter Input Capacitance Output Capacitance Test Conditions VIN = 0V VOUT = 0V Max 7 9 Unit pF

Symbol ICC Parameter Dynamic Operating Current Temperature Range Commercial Industrial Unit mA

*Tested with outputs open and all address and data inputs changing at the maximum write-cycle rate. The device is continuously enabled for writing, i.e., CE2 VIH (min), CE1 and WE VIL (max), OE is high. Switching inputs are 0V and 3V. **As above but @ f=1 MHz and VIL/ VIH = 0V/ VCC.

(Over Recommended Operating Temperature & Supply Voltage) Symbol tRC tAA tAC tOH tLZ tHZ tOE tOLZ tOHZ tPU tPD Parameter Read Cycle Time Address Access Time Chip Enable Access Time Output Hold from Address Change Chip Enable to Output in Low Z Chip Disable to Output in High Z Output Enable Low to Data Valid Output Enable Low to Low Z Output Enable High to High Z Chip Enable to Power Up Time Chip Disable to Power Down Time Min Max Min Max Unit ns

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