P2V28S20ATP is organized x 4-bit Synchronous DRAM with LVTTL interface and P2V28S30ATP is organized x 8-bit and P2V28S40ATP is organized x 16-bit. All inputs and outputs are referenced to the rising edge of CLK. P2V28S20ATP,P2V28S30ATP and P2V28S40ATP achieve very high speed data rates to 166MHz, and are suitable for main memories or graphic memories in computer systems.

Active to Precharge Command Period (Min.) Row to Column Delay Access Time from CLK Ref /Active Command Period Operation Current (Single Bank) (Max.) (Min.) (Max.) V28S40D -7,-75,-8

- Single 3.3V �0.3V power supply - Max. Clock frequency -7:143MHz<3-3-3>/-75:133MHz<3-3-3>/-8:100MHz<2-2-2> - Fully synchronous operation referenced to clock rising edge - 4-bank operation controlled by BA0,BA1(Bank Address) - /CAS latency- 2/3 (programmable) - Burst length- 1/2/4/8/FP (programmable) - Burst type- Sequential and interleave burst (programmable) - Byte Control- DQML and DQMU (P2V28S40ATP) - Random column access - Auto precharge / All bank precharge controlled A10 - Auto and self refresh - 4096 refresh cycles /64ms - LVTTL Interface - Package 400-mil, 54-pin Thin Small Outline (TSOP II) with 0.8mm lead pitch

Vdd NC VddQ NC DQ0 VssQ NC VddQ NC DQ1 VssQ NC Vdd NC /WE /CAS /RAS /CS A2 A3 Vdd DQ0 VddQ NC DQ1 VssQ NC DQ2 VddQ NC DQ3 VssQ NC Vdd NC /WE /CAS /RAS /CS A2 A3 Vdd DQ0 VddQ DQ1 DQ2 VssQ DQ3 DQ4 VddQ DQ5 DQ6 VssQ DQ7 Vdd DQML /WE /CAS /RAS /CS A2 A3 Vdd Vss DQ15 VssQ DQ14 DQ13 VddQ DQ12 DQ11 VssQ DQ10 DQ9 VddQ DQ8 Vss NC DQMU CLK CKE A5 A4 Vss DQ7 VssQ NC DQ6 VddQ NC DQ5 VssQ NC DQ4 VddQ NC Vss NC DQM CLK CKE A5 A4 Vss NC VssQ NC DQ3 VddQ NC VssQ NC DQ2 VddQ NC Vss NC DQM CLK CKE A5 A4 Vss

: Master Clock : Clock Enable : Chip Select : Row Address Strobe : Column Address Strobe : Write Enable : Data I/O

: Output Disable / Write Mask : Address Input : Bank Address : Power Supply : Power Supply for Output : Ground : Ground for Output