FCC approved method of EMI attenuation Provides 15 dB EMI reduction Generates 1X, 2X, and 4X low EMI spread spectrum clock of the input frequency 4X: P2814 Optimized for input frequency range from to 40 MHz to 40 MHz to 40 MHz to 40 MHz Internal loop filter minimizes external components and board space Selectable spread options: Down Spread and Center Spread Low inherent cycle-to-cycle jitter Eight spread % selections: 3.3 V operating voltage CMOS/TTL compatible inputs and outputs Pinout compatible with Cypress CY25811, CY25812, and CY25814 Products available for industrial temperature range Available in 8-pin SOIC and TSSOP

Deviation and Spread Option Selections section). These combinations include Down Spread, Center Spread and percentage deviation range from to -3.50%. The P28xx reduces electromagnetic interference (EMI) at the clock source, allowing a system wide EMI reduction for all the down stream clocks and data dependent signals. The P28xx allows significant system cost savings by reducing the number of circuit board layers, ferrite beads, shielding, and other passive components that are traditionally required to pass EMI regulations. The P28xx modulates the output of a single PLL in order to "spread" the bandwidth of a synthesized clock, thereby decreasing the peak amplitudes of its harmonics. This results in significantly lower system EMI compared to the typical narrow band signal produced by oscillators and most clock generators. generation". The P28xx uses the most efficient and optimized modulation profile approved by the FCC and is implemented by using a proprietary all-digital method. Lowering EMI by increasing a signal's bandwidth is called "spread spectrum clock

The is a versatile spread spectrum frequency modulator designed specifically for input clock frequencies from to 40 MHz (see Input/Output Frequency Range Selections). The P28xx can generate an EMI reduced clock from crystal, ceramic resonator, or system clock. The P28xx-A and P28xx-B offer various combinations of spread options and percentage deviations (see Output Frequency

The P28xx is targeted towards EMI management for memory interfaces in mobile graphic chipsets and highspeed digital applications such as PC peripheral devices, consumer electronics, and embedded controller systems.

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Pin Description Pin# 2 3 SRS VDD XOUT P I ModOut FRS O I Pin Name XIN VSS D_C Type P I Description Connect to externally generated clock signal or crystal. Ground Connection. Connect to system ground. Digital logic input used to select Down (LOW) or Center (HIGH) Spread Options (see Output Frequency Deviation and Spread Option Selections). This pin has an internal pull-up resistor. Spread Range Selection. Digital logic input used to select frequency deviation (see Output Frequency Deviation and Spread Option Selections). This pin has an internal pull-up resistor. Spread Spectrum clock output (see Input/Output Frequency Range Selections and Output Frequency Deviation and Spread Option Selections). Frequency Range Selection. Digital logic input used to select input frequency range (see Input/Output Frequency Range Selections). This pin has an internal pull-up resistor. Connect +3.3 V Connect to crystal. No connect if externally generated clock signal is used.

Input/Output Frequency Range Selections Pin 6 FRS 0 1 Part number P2812 (2X) Input Output (MHz) Modulation rate Input frequency / 448 Input frequency / 896

Output Frequency Deviation and Spread Option Selections Part number Pin 3 D_C 0 1 Absolute Maximum Ratings Symbol VDD, VIN TSTG TA Parameter Voltage on any pin with respect to GND Storage temperature Operating temperature Rating to 70 Pin 4 SRS

Output frequency deviation and spread option -2.50% (Down) -3.50% (Down) +/-1.25% (Center) +/-1.75% (Center) -1.25% (Down) -1.75% (Down) +/-0.625% (Center) +/-0.875% (Center)

DC Electrical Characteristics 25� C Symbol VIL VIH IIL IIH IXOL IXOH VOL VOH IDD ICC VDD tON ZOUT Parameter Input Low Voltage Input High Voltage Input low Current (inputs D_C, SRS, and FRS) Input High Current XOUT Output Low Current 0.4V, VDD = 3.3V) XOUT Output High Current 2.5V, VDD = 3.3V) Output Low Voltage (VDD=3.3V, IOL = 20 mA) Output High Voltage (VDD=3.3V, IOH = 20 mA) Static Supply Current Standby Mode Dynamic Supply Current Normal Mode (3.3V and 25 pF probe loading) Operating Voltage Power Up Time (First locked clock cycle after power up) Clock Output Impedance Min GND fIN-min � Typ Max 0.8 VDD fIN-max � Unit V mS