High-performance, cost-effective, �m (OR3C) and (OR3T) 4-level metal technology, or 5-input look-up table delay 1.1 ns with -7 speed grade in 0.3 �m). Same basic architecture as lower-voltage, advanced process technology Series 3 architectures. (See ORCA Series 3L FPGA documentation.) to 186,000 usable gates. to 452 user I/Os. (OR3Txxx I/Os are 5 V tolerant to allow interconnection to both 3.3 V and 5 V devices, selectable on a per-pin basis.) Pin selectable I/O clamping diodes provide 3.3 V PCI compliance and 5 V tolerance on OR3Txxx devices. Twin-quad programmable function unit (PFU) architecture with eight 16-bit look-up tables (LUTs) per PFU, organized in two nibbles for use in nibble- or byte-wide functions. Allows for mixed arithmetic and logic functions in a single PFU. Nine user registers per PFU, one following each LUT, plus one extra. All have programmable clock enable and local set/reset, plus a global set/reset that can be disabled per PFU. Flexible input structure (FINS) of the PFUs provides a routability enhancement for LUTs with shared inputs and the logic flexibility of LUTs with independent inputs. Fast-carry logic and routing to adjacent PFUs for nibble-, byte-wide, or longer arithmetic functions, with the option to register the PFU carry-out. Softwired LUTs (SWL) allow fast cascading up to three levels of LUT logic in a single PFU for to 40% speed improvement. Supplemental logic and interconnect cell (SLIC) provides 3-statable buffers, to 10-bit decoder, and PAL*-like AND-OR with optional INVERT in each programmable

logic cell (PLC), with over 50% speed improvement typical. Abundant hierarchical routing resources based on routing two data nibbles and two control lines per set provide for faster place and route implementations and less routing delay. TTL or CMOS input levels programmable per pin for the (5.0 V) devices. Individually programmable drive capability: sink/6 mA source sink/3 mA source. Built-in boundary scan (IEEE 1149.1 JTAG) and TS_ALL testability function to 3-state all I/O pins. Enhanced system clock routing for low skew, high-speed clocks originating on-chip or at any I/O. Up to four ExpressCLK inputs allow extremely fast clocking of signals on- and off-chip plus access to internal general clock routing. StopCLK feature to glitchlessly stop/start ExpressCLKs independently by user command. Programmable I/O (PIO) has: Fast-capture input latch and input flip-flop (FF) latch for reduced input setup time and zero hold time. Capability to (de)multiplex I/O signals. Fast access to SLIC for decodes and PAL-like functions. Output FF and two-signal function generator to reduce CLK to output propagation delay. Fast open-drain dive capability Capability to register 3-state enable signal. Baseline FPGA family used in Series 3+ FPSCs (field programmable system chips) which combine FPGA logic and standard cell logic on one device.

* PAL is a trademark of Advanced Micro Devices, Inc. IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc.

Device OR3C/3T80 OR3T125 System Gates 116K 186K LUTs Registers Max User RAM 62K 100K User I/Os Array Size x 28 Process Technology �m/4 LM

The system gate counts range from a logic-only gate count to a gate count assuming 30% of the PFUs/SLICs being used as RAMs. The logic-only gate count includes each PFU/SLIC (counted as 108 gates per PFU/SLIC), including 12 gates per LUT/FF pair (eight per PFU), and 12 gates per SLIC/FF pair (one per PFU). Each of the four PIOs per PIC is counted as 16 gates (two FFs, fast-capture latch, output logic, CLK drivers, and I/O buffers). PFUs used as RAM are counted at four gates per bit, with each PFU capable of implementing x 4 RAM (or 512 gates) per PFU.

Features......................................................................1 System-Level Features................................................6 Description...................................................................7 FPGA Overview........................................................7 PLC Logic..................................................................7 PIC Logic...................................................................8 System Routing......................................................................8 Configuration.............................................................8 ORCA Foundry Development System......................9 Architecture.................................................................9 Programmable Logic Cells........................................11 Programmable Function Unit..................................11 Look-Up Table Operating Modes............................13 Supplemental Logic and Interconnect Cell (SLIC)..21 PLC Latches/Flip-Flops...........................................25 PLC Routing Resources..........................................27 PLC Architectural Description.................................34 Programmable Input/Output 5 V Tolerant I/O.......................................................37 PCI Compliant Inputs......................................................................38 Outputs....................................................................41 PIC Routing Resources...........................................44 PIC Architectural Description..................................45 High-Level Routing Resources..................................47 Interquad Routing....................................................47 Programmable Corner Cell Routing........................48 PIC Interquad (MID) Routing...................................49 Clock Distribution Network........................................50 PFU Clock Sources.................................................50 Clock Distribution in the PLC Array.........................51 Clock Sources to the PLC Array.............................52 Clocks in the PICs...................................................52 ExpressCLK Inputs.................................................53 Selecting Clock Input Pins......................................53 Special Function Blocks............................................54 Single Function Blocks............................................54 Boundary Scan........................................................57 Microprocessor Interface (MPI).................................64 PowerPC i960 System............................................................66 MPI Interface to FPGA............................................67 MPI Setup and Control............................................68 Programmable Clock Manager (PCM)......................72 PCM Registers........................................................73 Delay-Locked Loop (DLL) Mode.............................75 Phase-Locked Loop (PLL) Mode............................76 PCM/FPGA Internal Interface.................................79 PCM Operation.......................................................79 PCM Detailed Programming...................................80 PCM Applications....................................................83 2

PCM Cautions........................................................ 84 FPGA States of Operation........................................ 85 Initialization............................................................. 85 Configuration.......................................................... 86 Start-Up.................................................................. 87 Reconfiguration...................................................... 88 Partial Reconfiguration........................................... 88 Other Configuration Options................................... 88 Configuration Data Format...................................... 89 Using ORCA Foundry to Generate Configuration RAM Data....................................... 89 Configuration Data Frame...................................... 89 Bit Stream Error Checking...................................... 91 FPGA Configuration Modes...................................... 92 Master Parallel Mode............................................. 92 Master Serial Mode................................................ 93 Asynchronous Peripheral Mode............................. 94 Microprocessor Interface (MPI) Mode.................... 94 Slave Serial Mode.................................................. 97 Slave Parallel Mode............................................... 97 Daisy-Chaining....................................................... 98 Daisy-Chaining with Boundary Scan...................... 99 Absolute Maximum Ratings.................................... 100 Recommended Operating Conditions.................. 100 Electrical Characteristics........................................ 101 Timing Characteristics............................................ 103 Description........................................................... 103 PFU Timing......................................................... 104 PLC Timing........................................................... 111 SLIC Timing.......................................................... 111 PIO Timing........................................................... 112 Special Function Blocks Timing........................... 115 Clock Timing......................................................... 123 Configuration Timing............................................ 133 Readback Timing................................................. 142 Input/Output Buffer Measurement Conditions........ 143 Output Buffer Characteristics................................. OR3Txxx.............................................................. 145 Estimating Power Dissipation................................. 146 OR3Txxx (Preliminary Information)...................... 147 Pin Information....................................................... 149 Pin Descriptions................................................... 149 Package Compatibility.......................................... 153 Compatibility with OR2C/TxxA Series.................. 154 Package Thermal Characteristics........................... 194 JA....................................................................... 194 JC...................................................................... 194 JC...................................................................... 194 JB...................................................................... 194 FPGA Maximum Junction Temperature............... 195 Lucent Technologies Inc.

Package Coplanarity...............................................196 Package Parasitics..................................................196 Package Outline Diagrams......................................197 Terms and 600-Pin EBGA.......................................................205 Ordering Information................................................206 Index........................................................................207 Tables Table 1. ORCA Series 3 (3C and 3T) FPGAs............ 2 Table 2. ORCA Series 3 System Performance.......... 6 Table 3. Look-Up Table Operating Modes............... 13 Table 4. Control Input Functionality.......................... 14 Table 5. Ripple Mode Equality Comparator Functions and Outputs............................................ 18 Table 6. SLIC Modes................................................ 21 Table 7. Configuration RAM Controlled Latch/Flip-Flop Operation........................................ 25 Table 8. Inter-PLC Routing Resources..................... 31 Table 9. PIO Options................................................ 37 Table 10. PIO Logic Options.................................... 43 Table 11. PIO Register Control Signals.................... 43 Table 12. Readback Options.................................... 54 Table 13. Boundary-Scan Instructions..................... 58 Table 14. Boundary-Scan ID Code........................... 59 Table 15. TAP Controller Input/Outputs................... 61 Table 16. PowerPC/MPI Configuration..................... 65 Table 17. i960/MPI Configuration............................. 66 Table 18. MPI Internal Interface Signals.................. 67 Table 19. MPI Setup and Control Registers............. 68 Table 20. MPI Setup and Control Registers Description............................................................... 68 Table 21. MPI Control Register 2............................. 69 Table 22. Status Register......................................... 70 Table 23. Device ID Code........................................ 71 Table 24. Series 3 Family and Device ID Values..... 71 Table 25. ORCA Series 3 Device ID Descriptions.... 71 Table 26. PCM Registers......................................... 73 Table 27. DLL Mode Delay/1x Duty Cycle Programming Values............................................... 75 Table 28. DLL Mode Delay/2x Duty Cycle Programming Values............................................... 76 Table 29. PCM Oscillator Frequency Range 3Txxx. 78 Table 30. PCM Oscillator Frequency Range 3Cxx... 78 Table 31. PCM Control Registers............................. 80 Lucent Technologies Inc. Table 32. Configuration Frame Format and Contents..................................................................90 Table 33. Configuration Frame Size.........................91 Table 34. Configuration Modes................................92 Table 35. Absolute Maximum Ratings....................100 Table 36. Recommended Operating Conditions....100 Table 37. Electrical Characteristics........................101 Table 38. Derating for Commercial Devices (OR3Cxx)..............................................................103 Table 39. Derating for Industrial Devices (OR3Cxx) 103 Table 40. Derating for Commercial/Industrial Devices (OR3Txxx)...............................................103 Table 41. Combinatorial PFU Timing Characteristics.......................................................104 Table 42. Sequential PFU Timing Characteristics..106 Table 43. Ripple Mode PFU Timing Characteristics.......................................................107 Table 44. Synchronous Memory Write Characteristics.......................................................109 Table 45. Synchronous Memory Read Characteristics.......................................................110 Table 46. PFU Output MUX and Direct Routing Timing Characteristics...........................................111 Table 47. Supplemental Logic and Interconnect Cell (SLIC) Timing Characteristics........................111 Table 48. Programmable I/O (PIO) Timing Characteristics.......................................................112 Table 49. Microprocessor Interface (MPI) Timing Characteristics.......................................................115 Table 50. Programmable Clock Manager (PCM) Timing Characteristics (Preliminary Information)..121 Table 51. Boundary-Scan Timing Characteristics..122 Table 52. ExpressCLK (ECLK) and Fast Clock (FCLK) Timing Characteristics..............................123 Table 53. General-Purpose Clock Timing Characteristics (Internally Generated Clock).........124 Table 54. OR3Cxx ExpressCLK to Output Delay (Pin-to-Pin)............................................................125 Table 55. OR3Cxx Fast Clock (FCLK) to Output Delay (Pin-to-Pin)..................................................126 Table 56. OR3Cxx General System Clock (SCLK) to Output Delay (Pin-to-Pin)..................................127 Table 57. OR3C/Txxx Input to ExpressCLK (ECLK) Fast-Capture Setup/Hold Time (Pin-to-Pin)..........128 Table 58. OR3C/Txxx Input to Fast Clock Setup/Hold Time (Pin-to-Pin)................................130 Table 59. OR3C/Txxx Input to General System Clock (SCLK) Setup/Hold Time (Pin-to-Pin)..........132 Table 60. General Configuration Mode Timing Characteristics.......................................................133 Table 61. Master Serial Configuration Mode Timing 3