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PHILIPS
74F5074
Synchronizing dual D-type flip-flop/clock
driver
Product specification
IC15 Data Handbook
1990 Sep 14
INTEGRATED CIRCUITS
:::
Philips Semiconductors Product specification
74F5074Synchronizing dual D-type flip-flop/clock driver
2
September 14, 1990 853-1391 00419
FEATURES
•Metastable immune characteristics
•Output skew guaranteed less than 1.5ns
•High source current (IOH = 15mA) ideal for clock driver
applications
•Pin out compatible with 74F74
•74F50728 for synchronizing cascaded D–type flip–flop
•See 74F50729 for synchronizing dual D–type flip–flop with
edge–triggered set and reset
•See 74F50109 for synchronizing dual J–K positive
edge–triggered flip–flop
•Industrial temperature range available (–40°C to +85°C)
TYPE TYPICAL fmax TYPICAL SUPPLY
CURRENT (TOTAL)
74F5074 120MHz 20mA
ORDERING INFORMATION
ORDER CODE
DESCRIPTION COMMERCIAL RANGE PKG DWG #
VCC = 5V ±10%,
Tamb = 0°C to +70°C
14–pin plastic DIP N74F5074N SOT27-1
14–pin plastic SO N74F5074D SOT108-1
INPUT AND OUTPUT LOADING
AND FAN OUT TABLE
PINS DESCRIPTION
74F
(U.L.)
HIGH/
LOW
LOAD VAL-
UE HIGH/
LOW
D0, D1 Data inputs 1.0/0.417 20µA/250µA
CP0, CP1 Clock inputs (active
rising edge) 1.0/1.0 20µA/20µA
SD0, SD1 Set inputs (active low) 1.0/1.0 20µA/20µA
RD0, RD1 Reset inputs (active
low) 1.0/1.0 20µA/20µA
Q0, Q1, Q0,
Q1 Data outputs 750/33 15mA/20mA
NOTE: One (1.0) FAST unit load is defined as: 20µA in the high
state and 0.6mA in the low state.
PIN CONFIGURATION
14
13
12
11
10
9
87
6
5
4
3
2
1
GND
VCC
SD1
Q1
Q1
CP1
RD1
D1
RD0
D0
Q0
CP0
Q0
SD0
SF00582
IEC/IEEE SYMBOL
D1D0
Q0 Q0 Q1 Q1
56 98
212
VCC = Pin 14
GND = Pin 7
CP0
SD0
RD0
CP1
SD1
RD1
3
4
1
11
10
13
SF00583
LOGIC SYMBOL
4
3
2
1
10
11
12
13
3
6
9
8
&
S
S
C1
C2
1D
2D
R
R
SF00584
Philips Semiconductors Product specification
74F5074Synchronizing dual D-type flip-flop/clock driver
September 14, 1990 3
LOGIC DIAGRAM
VCC = Pin 14
GND = Pin 7
4, 10
3, 11
SD
CP
Q
5, 9
SF00585
2, 12
1, 13
6, 8 Q
D
RD
DESCRIPTION
The 74F5074 is a dual positive edge–triggered D–type featuring
individual data, clock, set and reset inputs; also true and
complementary outputs.
Set (SDn) and reset (RDn) are asynchronous active low inputs and
operate independently of the clock (CPn) input. Data must be stable
just one setup time prior to the low–to–high transition of the clock for
guaranteed propagation delays.
Clock triggering occurs at a voltage level and is not directly related
to the transition time of the positive–going pulse. Following the hold
time interval, data at the Dn input may be changed without affecting
the levels of the output.
The 74F5074 is designed so that the outputs can never display a
metastable state due to setup and hold time violations. If setup time
and hold time are violated the propagation delays may be extended
beyond the specifications but the outputs will not glitch or display a
metastable state. Typical metastability parameters for the 74F5074
are: τ ≅ 135ps and To ≅ 9.8 X 106 sec where τ represents a
function of the rate at which a latch in a metastable state resolves
that condition and T0 represents a function of the measurement of
the propensity of a latch to enter a metastable state.
Metastable Immune Characteristics
Philips Semiconductor uses the term ’metastable immune’ to
describe characteristics of some of the products in its family.
Specifically the 74F50XXX family presently consist of 4 products
which will not glitch or display an output anomaly under any
circumstances including setup and hold time violations. This claim is
easily verified on the 74F5074. By running two independent signal
generators (see Fig. 1) at nearly the same frequency (in this case
10MHz clock and 10.02 MHz data) the device–under–test can be
often be driven into a metastable state. If the Q output is then used
to trigger a digital scope set to infinite persistence the Q output will
build a waveform. An experiment was run by continuously operating
the devices in the region where metastability will occur.
When the device–under–test is a 74F74 (which was not designed
with metastable immune characteristics) the waveform will appear
as in Fig. 2.
Figure 2 shows clearly that the Q output can vary in time with
respect to the Q trigger point. This also implies that the Q or Q
output waveshapes may be distorted. This can be verified on an
analog scope with a charge plate CRT. Perhaps of even greater
interest are the dots running along the 3.5V volt line in the upper
right hand quadrant. These show that the Q output did not change
state even though the Q output glitched to at least 1.5 volts, the
trigger point of the scope.
When the device–under–test is a metastable immune part, such as
the 74F5074, the waveform will appear as in Fig. 3. The 74F5074 Q
output will appear as in Fig. 3. The 74F5074 Q output will not vary
with respect to the Q trigger point even when the a part is driven into
a metastable state. Any tendency towards internal metastability is
resolved by Philips Semiconductor patented circuitry. If a metastable
event occurs within the flop the only outward manifestation of the
event will be an increased clock–to–Q/Q propagation delay. This
propagation delay is, of course, a function of the metastability
characteristics of the part defined by τ and T0.
The metastability characteristics of the 74F5074 and related part
types represent state–of–the–art TTL technology.
After determining the T0 and t of the flop, calculating the mean time
between failures (MTBF) is simple. Suppose a designer wants to
use the 74F5074 for synchronizing asynchronous data that is
arriving at 10MHz (as measured by a frequency counter), has a
clock frequency of 50MHz, and has decided that he would like to
sample the output of the 74F5074 10 nanoseconds after the clock
edge. He simply plugs his number into the equation below:
MTBF = e(t’/t)/ TofCfI
In this formula, fC is the frequency of the clock, fI is the average
input event frequency, and t’ is the time after the clock pulse that the
output is sampled (t’ < h, h being the normal propagation delay). In
this situation the fI will be twice the data frequency of 20 MHz
because input events consist of both of low and high transitions.
Multiplying fI by fC gives an answer of 1015 Hz2. From Fig. 4 it is
clear that the MTBF is greater than 1010 seconds. Using the above
formula the actual MTBF is 1.51 X 1010 seconds or about 480 years.
DQ
Q
CP
TRIGGER
DIGITAL
SCOPE
INPUT
SIGNAL GENERATOR
SF00586
SIGNAL GENERATOR
Figure 1. Test Set-up
Philips Semiconductors Product specification
74F5074Synchronizing dual D-type flip-flop/clock driver
September 14, 1990 4
COMPARISON OF METASTABLE IMMUNE AND NON–IMMUNE CHARACTERISTICS
4
3
2
1
0
Time base = 2.00ns/div Trigger level = 1.5 Volts Trigger slope = positive
SF00587
Figure 2. 74F74 Q Output triggered by Q output, set-up and hold times violated
3
2
1
0
Time base = 2.00ns/div Trigger level = 1.5 Volts Trigger slope = positive
SF00588
Figure 3. 74F74 Q Output triggered by Q output, set-up and hold times violated
X
T
1
Philips Semiconductors Product specification
74F5074Synchronizing dual D-type flip-flop/clock driver
September 14, 1990 5
MEAN TIME BETWEEN FAILURES (MTBF) VERSUS t’
78910
1012
1011
1010
109
108
107
106
1014
1015 = fCfI
t’ in nanoseconds
MTBF in seconds
one year
1061081010 1012
one week
10,000 years
100 years
SF00589
NOTE: VCC = 5V, Tamb = 25°C, τ =135ps, To = 9.8 X 106 sec Figure 4.
TYPICAL VALUES FOR τ AND T0 AT VARIOUS VCCS AND TEMPERATURES
Tamb = 0°C
Tamb = 25°C
Tamb = 70°C
VCC τT0τT0τT0
5.5V 125ps 1.0 X 109 sec 138ps 5.4 X 106 sec 160ps 1.7 X 105 sec
5.0V 115ps 1.3 X 1010 sec 135ps 9.8 X 106 sec 167ps 3.9 X 104 sec
4.5V 115ps 3.4 X 1013 sec 132ps 5.1 X 108 sec 175ps 7.3 X 104 sec
FUNCTION TABLE
INPUTS OUTPUTS OPERATING
SD RD CP D Q Q MODE
L H X X H L Asynchronous set
H L X X L H Asynchronous reset
L L X X H H Undetermined*
H H ↑h H L Load “1”
H H ↑l L H Load “0”
H H ↑X NC NC Hold
NOTES:
H = High voltage level
h = High voltage level one setup time prior to low–to–high clock transition
L = Low voltage level
l = Low voltage level one setup time prior to low–to–high clock transition
NC= No change from the previous setup
X = Don’t care
↑= Low–to–high clock transition
↑= Not low–to–high clock transition
* = This setup is unstable and will change when either set or reset return to the high level
Philips Semiconductors Product specification
74F5074Synchronizing dual D-type flip-flop/clock driver
September 14, 1990 6
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the
operating free air temperature range.)
SYMBOL PARAMETER RATING UNIT
VCC Supply voltage –0.5 to +7.0 V
VIN Input voltage –0.5 to +7.0 V
IIN Input current –30 to +5 mA
VOUT Voltage applied to output in high output state –0.5 to VCC V
IOUT Current applied to output in low output state 40 mA
Tamb Operating free air temperature range 0 to +70 °C
Tstg Storage temperature range –65 to +150 °C
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER LIMITS TA = –40 to +85°C
MIN NOM MAX UNIT
VCC Supply voltage 4.5 5.0 5.5 V
VIH High–level input voltage 2.0 V
VIL Low–level input voltage 0.8 V
IIk Input clamp current –18 mA
IOH High–level output current VCC ± 10% –12 mA
VCC ± 5% –15 mA
IOL Low–level output current 20 mA
Tamb Operating free air temperature range 0 +70 °C
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL PARAMETER TEST LIMITS UNIT
CONDITIONS1MIN TYP2MAX
VOH High–level output voltage VCC = MIN, VIL =
MAX, IOH = MAX ±10%VCC 2.5 V
VIH = MIN ±5%VCC 2.7 3.4 V
VOL Low–level output voltage VCC = MIN, VIL =
MAX, IOL = MAX ±10%VCC 0.30 0.50 V
VIH = MIN ±5%VCC 0.30 0.50 V
VIK Input clamp voltage VCC = MIN, II = IIK -0.73 -1.2 V
IIInput current at maximum input voltage VCC = MAX, VI = 7.0V 100 µA
IIH High–level input current VCC = MAX, VI = 2.7V 20 µA
IIL Low–level input current Dn VCC = MAX, VI = 0.5V -250 µA
CPn, SDn, RDn VCC = MAX, VI = 0.5V -20 µA
IOS Short circuit output current3VCC = MAX -60 -150 mA
ICC Supply current4 (total) VCC = MAX 20 30 mA
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at VCC = 5V, Tamb = 25°C.
3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, IOS tests should be performed last.
4. Measure ICC with the clock input grounded and all outputs open, then with Q and Q outputs high in turn.
Philips Semiconductors Product specification
74F5074Synchronizing dual D-type flip-flop/clock driver
September 14, 1990 7
AC ELECTRICAL CHARACTERISTICS
LIMITS
Tamb = +25°C Tamb = 0°C to +70°C
SYMBOL PARAMETER TEST VCC = +5.0V VCC = +5.0V ± 10% UNIT
CONDITION CL = 50pF,
RL = 500ΩCL = 50pF,
RL = 500Ω
MIN TYP MAX MIN MAX
fmax Maximum clock frequency Waveform 1 105 120 90 ns
tPLH
tPHL
Propagation delay
CPn to Qn or Qn Waveform 1 2.0
2.0 3.9
3.9 6.0
6.0 1.5
2.0 6.5
6.5 ns
tPLH
tPHL
Propagation delay
SDn, RDn to Qn or Qn Waveform 2 3.0
3.0 4.5
5.0 7.5
7.5 2.5
2.5 8.0
8.0 ns
tsk(o) Output skew1,2 Waveform 4 1.5 1.5 ns
NOTES:
1. |tPN actual – tPM actual| for any output compared to any other output where N and M are either LH or HL.
2. Skew times are valid only under same test conditions (temperature, VCC, loading, etc.,).
AC SETUP REQUIREMENTS
LIMITS
Tamb = +25°C Tamb = 0°C to +70°C
SYMBOL PARAMETER TEST VCC = +5.0V VCC = +5.0V ± 10% UNIT
CONDITION CL = 50pF,
RL = 500ΩCL = 50pF,
RL = 500Ω
MIN TYP MAX MIN MAX
tsu (H)
tsu(L) Setup time, high or low
Dn to CPn Waveform 1 1.5
1.5 2.0
2.0 ns
th (H)
th (L) Hold time, high or low
Dn to CPn Waveform 1 1.0
1.0 1.5
1.5 ns
tw (H)
tw (L) CPn pulse width,
high or low Waveform 1 3.0
4.0 3.0
4.5 ns
tw (L) SDn or RDn pulse width, low Waveform 2 3.0 4.0 ns
trec Recovery time
SDn or RDn to CPn Waveform 3 3.0 3.5 ns
a
TY
Philips Semiconductors Product specification
74F5074Synchronizing dual D-type flip-flop/clock driver
September 14, 1990 8
AC WAVEFORMS
VM
VM
CPn
VMVMVMVM
VMVM
tsu(H) th(H)
Dn
Qn
VM
tw(H)
1/fmax
tsu(L) th(L)
VM
VM
tPLH
Qn
tw(L)
tPHL
tPHL
tPLH
SF00049
Waveform 1. Propagation delay for data to output, data
setup time and hold times, and clock
width, and maximum clock frequency
SDn or RDn VM
VM
trec
CPn
SF00051
Waveform 3. Recovery time for set or reset to output
VM
VM
RDn VM
Qn
VM
VM
VM
tPLH
Qn
tw(L)
tPHL
tPHL
tPLH
SDn VM
VM
tw(L)
SF00050
Waveform 2. Propagation delay for set and reset to output,
set and reset pulse width
Qn, QnVM
VM
tsk(o)
Qn, Qn
SF00590
Waveform 4. Output skew
NOTES:
For all waveforms, VM = 1.5V.
The shaded areas indicate when the input is permitted to change for predictable output performance.
TEST CIRCUIT AND WAVEFORMS
tw90%
VM
10%
90%
VM
10%
90%
VM
10%
90%
VM
10%
NEGATIVE
PULSE
POSITIVE
PULSE
tw
AMP (V)
0V
0V
tTHL (tf )
INPUT PULSE REQUIREMENTS
rep. rate twtTLH tTHL
1MHz 500ns 2.5ns 2.5ns
Input Pulse Definition
VCC
family
74F
D.U.T.
PULSE
GENERATOR
RL
CL
RT
VIN VOUT
Test Circuit for Totem-Pole Outputs
DEFINITIONS:
RL= Load resistor;
see AC ELECTRICAL CHARACTERISTICS for value.
CL= Load capacitance includes jig and probe capacitance;
see AC ELECTRICAL CHARACTERISTICS for value.
RT= Termination resistance should be equal to ZOUT of
pulse generators.
tTHL (tf )
tTLH (tr )
tTLH (tr )
AMP (V)
amplitude
3.0V 1.5V
VM
SF00006
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DIMENSIONS (inch dimemionl we derived «om the origin-l mm aimenmnep
UNIT mix '3'}. "fig“ b b. c D") E"1 o o. L w NEE)
mm 4‘2 0f" 32 Hi 3233 333 1:23 :23 w 7‘62 333 3:3 ‘57: 0254 22
mm: 017 0020 013 3m 83?; 83;; 8;; gig 010 030 3}; 3:3 3:: am 0037
N01:
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REFERENCES
3&3: .Ec MEG E.“ £13122:ng 'SSUEDATE
soTzn 05050; MoomAA a @ m
Philips Semiconductors Product specification
74F5074Synchronizing dual D-type flip-flop/clock driver
1990 Sep 14 9
DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1
Din I mdex
U 25 5mm
W
DIMENSIONS (inch dimensionaare derived «on. me original mm dimensions)
uurr "I; A. A2 A3 up c nm em . n: L L,, o v w y 20> e
m ‘75 3?: [2: "25 3.32 32?: 2;: 33 ‘27 3.: ‘05 33 3:; 0-25 0-25 0‘ 8.; 5.,
mmmmwmmmmmmmmmwwmmw
"ME
1 P‘asllc or metal pvotruslons om 15 mm maxumum pelsude are net lnc‘uded.
35%;: ,E M mm swam
son 05-1 076E065 MS-m 2A3 a @ m
Philips Semiconductors Product specification
74F5074Synchronizing dual D-type flip-flop/clock driver
1990 Sep 14 10
SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1
Philips Semiconductors Product specification
74F5074Synchronizing dual D-type flip-flop/clock driver
1990 Sep 14 11
NOTES
Dommentmdernumber 93977750705207
Laémnwbm
PH I LI PS
Philips Semiconductors Product specification
74F5074Synchronizing dual D-type flip-flop/clock driver
yyyy mmm dd 12
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
print code Date of release: 10-98
Document order number: 9397-750-05207
Data sheet
status
Objective
specification
Preliminary
specification
Product
specification
Product
status
Development
Qualification
Production
Definition [1]
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
Data sheet status
[1] Please consult the most recently issued datasheet before initiating or completing a design.
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