MTP1N100E

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MTP1N100E/D ™ Data Sheet TMOS E-FET.™ Power Field Effect Transistor Designer's MTP1N100E Motorola Preferred Device N–Channel Enhancement–Mode Silicon Gate This high voltage MOSFET uses an advanced termination scheme to provide enhanced voltage–blocking capability without degrading pe

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rformance over time. In addition, this advanced TMOS E–FET is designed to withstand high energy in the avalanche and commutation modes. The new energy efficient design also offers a drain–to–source diode with a fast recovery time. Designed for high voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. • Robust High Voltage Termination • Avalanche Energy Specified • Source–to–Drain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode • Diode is Characterized for Use in Bridge Circuits • IDSS and VDS(on) Specified at Elevated Temperature G S TMOS POWER FET 1.0 AMPERES 1000 VOLTS RDS(on) = 9.0 OHM ® D CASE 221A–06, Style 5 TO–220AB MAXIMUM RATINGS (TC = 25°C unless otherwise noted) Rating Drain–Source Voltage Drain–Gate Voltage (RGS = 1.0 MΩ) Gate–Source Voltage — Continuous Gate–Source Voltage — Non–Repetitive (tp ≤ 10 ms) Drain Current — Continuous Drain Current — Continuous @ 100°C Drain Current — Single Pulse (tp ≤ 10 µs) Total Power Dissipation Derate above 25°C Operating and Storage Temperature Range Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C (VDD = 100 Vdc, VGS = 10 Vdc, IL = 3.0 Apk, L = 10 mH, RG = 25 Ω) Thermal Resistance — Junction to Case Thermal Resistance — Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds Symbol VDSS VDGR VGS VGSM ID ID IDM PD TJ, Tstg EAS RθJC RθJA TL Value 1000 1000 ± 20 ± 40 1.0 0.8 3.0 75 0.6 – 55 to 150 45 1.67 62.5 260 Unit Vdc Vdc Vdc Vpk Adc Apk Watts W/°C °C mJ °C/W °C Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit curves — representing boundaries on device characteristics — are given to facilitate “worst case” design. E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc. Preferred devices are Motorola recommended choices for future use and best overall value. REV 2 TMOS © Motorola Motorola, Inc. 1995 Power MOSFET Transistor Device Data 1 MTP1N100E ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Characteristic OFF CHARACTERISTICS Drain–Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 µAdc) Temperature Coeffici