M11B11664A

(OLWH07 DRAM FEATURES y X16 organization y EDO (Extended Data-Output) access mode y 2 CAS Byte/Word Read/Write operation y Single 5V ( ± 10%) power supply y TTL-compatible inputs and outputs y 256-cycle refresh in 4ms y Refresh modes : RAS only, CAS BEFORE RAS (CBR) and HIDDEN y JEDEC standard pinout y Key AC Parameter tRAC tCAC tRC tPC -25

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25 8 43 10 -30 30 9 55 12 -35 35 10 65 14 -40 40 11 75 16 M11B11664A 64 K x 16 DRAM EDO PAGE MODE ORDERING INFORMATION - PACKAGE 40-pin 400mil SOJ 44 / 40-pin 400mil TSOP (TypeII) PRODUCT NO. M11B11664A-25J M11B11664A-30J M11B11664A-35J M11B11664A-40J M11B11664A-25T M11B11664A-30T M11B11664A-35T M11B11664A-40T PACKING TYPE SOJ TSOPII GENERAL DESCRIPTION The M11B11664A is a randomly accessed solid state memory, organized as 65,536 x 16 bits device. It offers Extended Data-Output , 5V( ± 10%) single power supply. Access time (-25,-30,-35,-40) and package type (SOJ, TSOP II) are optional features of this family. All these family have CAS - before - RAS , RAS -only refresh and Hidden refresh capabilities. Two access modes are supported by this device : Byte access and Word access. Use only one of the two CAS and leave the other staying high will result in a BYTE access. WORD access happens when two CAS ( CASL , CASH ) are used. CASL transiting low during READ or WRITE cycle will output or input data into the lower byte (IO0~IO7), and CASH transiting low will output or input data into the upper byte (IO8~15). PIN ASSIGNMENT SOJ Top View VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 NC NC WE RAS NC A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 VSS 39 I/O15 38 I/O14 37 I/O13 36 I/O12 35 VSS 34 I/O11 33 I/O10 32 I/O9 31 I/O8 30 N C 29 CASL 28 CASH 27 OE 26 N C 25 A7 24 A6 23 A5 22 A4 21 VSS TSOP (TypeII) Top View VCC I/O0 I/O1 I/O2 I/O3 VC C I/O4 I/O5 I/O6 I/O7 NC NC WE RAS NC A0 A1 A2 A3 VC C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 VSS 39 I/O15 38 I/O14 37 I/O13 36 I/O12 35 VSS 34 I/O11 33 I/O10 32 I/O9 31 I/O8 30 N C 29 CASL 28 CASH 27 OE 26 N C 25 A7 24 A6 23 A5 22 A4 21 VSS Elite Memory Technology Inc Publication Date : Dec. 2000 Revision : 1.3 1/15 (OLWH07 M11B11664A FUNCTIONAL BLOCK DIAGRAM WE RAS CASL CASH A0 A1 A2 A3 A4 A5 A6 A7 CONTROL LOGIC CLOCK GENERATOR COLUMN 8 ADDRESS BUFFER REFRESH CONTROLER REFRESH COUNTER 89 ROW. 8 ADDRESS BUFFERS(8) DATA-IN BUFFER IO0 16 : IO15 COLUMN 8 DECODER 256 16 SENSE AMPLIFIERS I/O GATING 8 256 x 16 DATA-OUT BUFFER 16 OE ROW DECODER 256 x256 x 16 256 MEMORY 8 ARRAY VBB GENERATOR VCC VSS PIN DESCRIPTIONS PIN NO. 16~19,22~25 14 28 29 13 27 2~5,7~10,31~34,36~39 1,6,20 21,35,40 11,12,15,30 PIN NAME A0~A7 RAS CASH CASL WE OE I/O0 ~ I/O15 VCC VSS NC TYPE DESCRIPTION Input Address Input Row Address : A0~A7 Column Address : A0~A7 Input Row Address