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LNK520P-TL Datasheet(PDF) 9 Page - Power Integrations, Inc. |
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LNK520P-TL Datasheet(HTML) 9 Page - Power Integrations, Inc. |
9 / 20 page 9 LNK520 E 2/05 Core gaps should be uniform. Uneven core gapping, especially with small gap sizes, may cause variation in the primary inductance with flux density (partial saturation) and make the constant current region non-linear. To verify uniform gapping, it is recommended that the primary current wave-shape be examined while feeding the supply from a DC source. The gradient is defined as di/dt = V/L and should remain constant throughout the MOSFET on time. Any change in gradient of the current ramp is an indication of uneven gapping. Measurements made using a LCR bridge should not be solely reliedupon;typicallytheseinstrumentsonlymeasureatcurrents of a few milliamps. This is insufficient to generate high enough flux densities in the core to show uneven gapping. For a typical EE16 or EE13 core using center leg gapping, a 0.08 mm gap allows a primary inductance tolerance of ±10% to be maintained in standard high volume production. This allows the EE13 to be used in designs up to 2.75 W with less than 300 mW no-load consumption. Using outer leg film gapping reducesinductancetoleranceto±7%orbetter,allowingdesigns up to 3 W. Using the larger EE16 allows for a 3 W output with center leg gapping. The EE13 core size may be attractive in designs were space is limited or if there is a cost advantage over the EE16. The transformer turns ratio should be selected to give a V OR (output voltage reflected through secondary to primary turns ratio) of 40 V to 80 V. Higher V OR increases the output power capability of LinkSwitch but also increases no-load power consumption. This allows even higher values to be used in designs where no-load power is not a concern. However care should be taken to ensure that the maximum temperature rise of the device is acceptable at the upper limit of the output characteristic when used in a charger application. In all cases, discontinuous mode operation should be maintained and note that the linearity of the CC region of the power supply output characteristic is influenced by the bias voltage. If this is an important aspect of the application, the output characteristic should be checked before finalizing the design. Output Characteristic Variation Boththedevicetoleranceandexternalcircuitgoverntheoverall tolerance of the LinkSwitch power supply output characteristic. Estimated peak power point tolerances for a LNK520, 2.75 W design are ±10% for voltage and ±24% for current limit for overall variation in high volume manufacturing. This includes device and transformer tolerances (±7.5% assumed) and line variation. Lower power designs may have poorer constant current linearity. As the output load reduces from the peak power point, the output voltage will tend to rise due to tracking errors compared to the load terminals. Sources of these errors include the output cable drop, output diode forward voltage and leakage inductance, which is the dominant cause. As the load reduces, the primary operating peak current reduces, together with the leakage inductance energy, which reduces the peak charging of the clamp capacitor. Atverylightorno-load,typicallylessthan2mAofoutputcurrent, theoutputvoltagerisesduetoleakageinductancepeakcharging of the secondary. This voltage rise can be reduced with a small preload with little change to no-load power consumption. The output voltage load variation can be improved across the whole load range by adding an optocoupler and secondary reference (Figure 6). The secondary reference is designed to only provide feedbackabovethenormalpeakpowerpointvoltagetomaintain the correct constant current characteristic. Component Selection The schematic shown in Figure 10 outlines the key components needed for a LinkSwitch supply. Clamp diode – D5 Diode D5 can be an ultra-fast (t rr < 50 ns), a fast (trr < 250 ns) or standard recovery diode with a voltage rating of 600 V or higher. Astandardrecoverydiodeisrecommendedasitimproves the CV characteristic, but should be a glass-passivated type (1N400xGP) to ensure a defined reverse recovery time. Clamp Capacitor – C4 Capacitor C4 should be in the range of 100 pF to 1000 pF, 500 V capacitor. A low cost ceramic disc is recommended. The tolerance of this part has a very minor effect on the output characteristic so any of the standard ±5%, ±10% or ±20% tolerances are acceptable. 330 pF is a good initial value, iterated with R1. Clamp Resistor – R1 The value of R1 is selected to be the highest value that still provides adequate margin to the DRAIN BV DSS rating at high line. As a general rule, the value of C4 should be minimized and R1 maximized. CONTROL Pin Capacitor – C5 Capacitor C5 is used during start-up to power LinkSwitch and sets the auto-restart frequency. For designs that have a battery load, this component should have a value of 0.22 µF and for resistive loads a value of 1 µF. This ensures there is sufficient time during start-up for the output voltage to reach regulation. Any capacitor type is acceptable with a voltage rating of 10 V or above. Bias Capacitor – C3 Capacitor C3 should be a 1 µF, 50 V electrolytic type. The voltage rating is consistent with the 20 V to 30 V seen across the bias winding. Lower values give poorer regulation. |
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