Details, datasheet, quote on part number: K4H510438B-TC/LB3
| Part | K4H510438B-TC/LB3 |
| Category | Memory => DRAM => DDR SDRAM => 512 Mb |
| Description | Description = K4H510438B DDR Sdram 512Mb B-die (x4, X8, X16) ;; Organization = 128Mx4 ;; Bank/ Interface = 4B/SSTL2 ;; Refresh = 8K/64ms ;; Speed = CC,B3,AA,A2,B0 ;; Package = 66TSOP2,54sTSOP2,60FBGA ;; Power = C,l ;; Production Status = Customer Sample(Q3'03) ;; Comments = DDR266/333 |
| Company | Samsung Semiconductor, Inc. |
| Datasheet | Download K4H510438B-TC/LB3 Datasheet |
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| Features, Applications |
Revision 0.0 (February, 2003) - First version for internal review Revision 1.0 (June, 2003) - updated DC Characteristics Revision 1.1 (August, 2003) - Deleted speed at K4H511632B and corrected typo. Double-data-rate architecture; two data transfers per clock cycle Bidirectional data strobe [DQ] (x4,x8) & [L(U)DQS] (x16) Four banks operation Differential clock inputs(CK and CK) DLL aligns DQ and DQS transition with CK transition MRS cycle with address key programs Read latency 2, 2.5 (clock) Burst length 4, 8) Burst type (sequential & interleave) All inputs except data & DM are sampled at the positive going edge of the system clock(CK) Data I/O transactions on both edges of data strobe Edge aligned data output, center aligned data input LDM,UDM for write masking only (x16) DM for write masking only (x4, x8) Auto & Self refresh 7.8us refresh interval(8K/64ms refresh) Maximum burst refresh cycle 8 66pin TSOP II package Part No. x 4 Org. Max Freq. SSTL2 66pin TSOP SSTL2 66pin TSOP SSTL2 66pin TSOP II Interface Package |
| Related products with the same datasheet |
| K4H510438B-TC/LA2 |
| K4H510438B-TC/LAA |
| K4H510438B-TC/LB0 |
| Some Part number from the same manufacture Samsung Semiconductor, Inc. |
| K4H510438M Description = K4H510438M 512Mb DDR Sdram ;; Organization = 128Mx4 ;; Bank/ Interface = 4B/SSTL2 ;; Refresh = 8K/64ms ;; Speed = A2,B0,A0 ;; Package = 66TSOP2 ;; Power = C,l ;; Production Status = Mass |
| K4H510638B Description = K4H510638B Stacked 512Mb (x4) DDR Sdram ;; Organization = 128Mx4 ;; Bank/ Interface = 4B/SSTL2 ;; Refresh = 8K/64ms ;; Speed = A2,B0,A0 ;; Package = 66TSOP2 ;; Power = C,l ;; Production Status |
| K4H510638C Description = K4H510638C Stacked 512Mb (x4) DDR Sdram ;; Organization = 128Mx4 ;; Bank/ Interface = 4B/SSTL2 ;; Refresh = 8K/64ms ;; Speed = B3,A2,B0,A0 ;; Package = 66TSOP2 ;; Power = C ;; Production |
| K4H510638D Description = K4H510638D The Data Sheet You Have Searched is Under Preparation. ;; Organization = 128Mx4 ;; Bank/ Interface = 4B/SSTL2 ;; Refresh = 8K/64ms ;; Speed = B3,A2,B0,A0 ;; Package = 66TSOP2 ;; Power |
| K4H510638E Description = K4H510638E DDR Sdram Stacked 512Mb E-die (x4/x8) ;; Organization = St.128Mx4 ;; Bank/ Interface = 4B/SSTL2 ;; Refresh = 8K/64ms ;; Speed = AA,A2,B0 ;; Package = 66TSOP2 ;; Power = C,l ;; Production |
| K4H510738E Description = K4H510738E DDR Sdram Stacked 512Mb E-die (x4/x8) ;; Organization = St.64Mx8 ;; Bank/ Interface = 4B/SSTL2 ;; Refresh = 8K/64ms ;; Speed = AA,A2,B0 ;; Package = 66TSOP2 ;; Power = C,l ;; Production |
| K4H510838B Description = K4H510838B DDR Sdram 512Mb B-die (x4, X8, X16) ;; Organization = 64Mx8 ;; Bank/ Interface = 4B/SSTL2 ;; Refresh = 8K/64ms ;; Speed = CC,C4,B3,AA,A2,B0 ;; Package = 66TSOP2,54sTSOP2,60FBGA |
| K4H510838C Description = K4H510838C DDP 512Mb(x8) DDR Sdram ;; Organization = 64Mx8 ;; Bank/ Interface = 4B/SSTL2 ;; Refresh = 8K/64ms ;; Speed = A2,B0,A0 ;; Package = 66TSOP2 ;; Power = C,l ;; Production Status |
| K4H510838M Description = K4H510838M 512Mb DDR Sdram ;; Organization = 64Mx8 ;; Bank/ Interface = 4B/SSTL2 ;; Refresh = 8K/64ms ;; Speed = A2,B0,A0 ;; Package = 66TSOP2 ;; Power = C,l ;; Production Status = Mass Production |
| K4H511638B Description = K4H511638B DDR Sdram 512Mb B-die (x4, X8, X16) ;; Organization = 32Mx16 ;; Bank/ Interface = 4B/SSTL2 ;; Refresh = 8K/64ms ;; Speed = CC,C4,B3,AA,A2,B0 ;; Package = 66TSOP2,60FBGA ;; Power |
| K4H511638D Description = K4H511638D 8Mx16Bitx4 Banks Double Data Rate Sdram ;; Organization = 32Mx16 ;; Bank/ Interface = 4B/SSTL2 ;; Refresh = 8K/64ms ;; Speed = B3,A2,B0,A0 ;; Package = 66TSOP2 ;; Power = C,l ;; Production |
| K4H560438B Description = K4H560438B 256Mb DDR Sdram ;; Organization = 64Mx4 ;; Bank/ Interface = 4B/SSTL2 ;; Refresh = 8K/64ms ;; Speed = A2,B0,A0 ;; Package = 66TSOP2 ;; Power = C,l ;; Production Status = Eol ;; Comments |
| K4H560438C Description = K4H560438C 256Mb C-die(x4,x8)DDR Sdram ;; Organization = 64Mx4 ;; Bank/ Interface = 4B/SSTL2 ;; Refresh = 8K/64ms ;; Speed = B3,A2,B0,A0 ;; Package = 66TSOP2 ;; Power = C,l ;; Production |
| K4H560438D Description = K4H560438D 256Mb D-die DDR Sdram ;; Organization = 64Mx4 ;; Bank/ Interface = 4B/SSTL2 ;; Refresh = 8K/64ms ;; Speed = B3,A2,B0,A0 ;; Package = 66TSOP2,54sTSOP2,60FBGA ;; Power = C,l ;; Production |
| K4H560438E Description = K4H560438E DDR Sdram 256Mb E-die (x4, X8) ;; Organization = 64Mx4 ;; Bank/ Interface = 4B/SSTL2 ;; Refresh = 8K/64ms ;; Speed = CC,C4,B3,AA,A2,B0 ;; Package = 66TSOP2,54sTSOP2,60FBGA ;; Power |
| K4H560838B Description = K4H560838B 256Mb DDR Sdram ;; Organization = 32Mx8 ;; Bank/ Interface = 4B/SSTL2 ;; Refresh = 8K/64ms ;; Speed = A2,B0,A0 ;; Package = 66TSOP2 ;; Power = C,l ;; Production Status = Eol ;; Comments |
| K4H560838C Description = K4H560838C 256Mb C-die(x4/x8)DDR Sdram ;; Organization = 32Mx8 ;; Bank/ Interface = 4B/SSTL2 ;; Refresh = 8K/64ms ;; Speed = B3,A2,B0,A0 ;; Package = 66TSOP2 ;; Power = C,l ;; Production |
| K4H560838D Description = K4H560838D 256Mb D-die DDR Sdram ;; Organization = 32Mx8 ;; Bank/ Interface = 4B/SSTL2 ;; Refresh = 8K/64ms ;; Speed = CC,C4,B3,A2,B0,A0 ;; Package = 66TSOP2,54sTSOP2,60FBGA ;; Power = C,l ;; Production |
| K4H560838E Description = K4H560838E DDR Sdram 256Mb E-die (x4, X8) ;; Organization = 32Mx8 ;; Bank/ Interface = 4B/SSTL2 ;; Refresh = 8K/64ms ;; Speed = CC,C4,B3,AA,A2,B0 ;; Package = 66TSOP2,54sTSOP2,60FBGA ;; Power |
| K4H560838F Description = K4H560838F DDR Sdram 256Mb F-die (x8, X16) ;; Organization = 32Mx8 ;; Bank/ Interface = 4B/SSTL2 ;; Refresh = 8K/64ms ;; Speed = CC,C4,B3,AA,A2,B0 ;; Package = 66TSOP2 ;; Power = C,l ;; Production |
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K7I323684M-FC20 : DDR II(CIO/SIO) Description = K7I323684M 1Mx36-bit, 2Mx18-bit, 4Mx8-bit Ddrii Cio b4 SRAM ;; Organization = 1Mx36 ;; VDD(V) = 1.8 ;; Access Time-tCD(ns) = 0.45,0.45,0.50 ;; Cycle Time(MHz) = 250,200,167 ;; I/o Voltage(V) = 1.5,1.8 ;; Package = 165FBGA ;; Production Status = Engineer Sample ;; Comments = CIO-4B KS5514B-06 : on Screen Display Processor M374S1723DTU-C7A : Unbuffered DIMM Description = M374S1723DTU 16Mx72 Sdram Dimm With Ecc Based on 16Mx8, 4Banks, 4K Refresh, 3.3V Synchronous DRAMs With SPD ;; Density(MB) = 128 ;; Organization = 16M X 72 ;; Bank/ Interface = 4B/LVTTL ;; Refresh = 4K/64ms ;; Speed = 7A,1H,1L ;; #of Pin = 168 ;; Power = C,l ;; Component Composition = M466S0823DT3 : SODIMM Description = M466S0823DT3 8M X 64 Sdram Sodimm Based on 8M X 8, 4Banks, 4K Refresh, 3.3V Synchronous DRAMs With SPD ;; Density(MB) = 64 ;; Organization = 8Mx64 ;; Bank/ Interface = 4B/LVTTL ;; Refresh = 4K/64ms ;; Speed = 10 ;; #of Pin = 144 ;; Power = L,c ;; Component Composition = (8Mx8)x8+EEPROM STD80FD6S : Standard Cell Libraries Description = STD80 0.5 Micron STD80 Standard Cell Library ;; Supply Voltage (V) = 5 ;; Technology(micron) = 0.5micron K4T51043QC-ZC(L)D5 : 512Mb C-die DDR2 SDRAM he 512Mb DDR2 SDRAM is organized as a 32Mbit x 4 I/Os x 4 banks device. This synchronous device achieves high speed doubledata-rate transfer rates of up to 800Mb/sec/pin (DDR2-800) for general applications. The chip is designed to comply with the following key DDR2 SDRAM fea KM62V256C : 32kx8 bit Low Power and Low Voltage CMOS Static RAM AT-SC-P-M6-10-A : RF/MICROWAVE FIXED ATTENUATOR, 20 dB INSERTION LOSS-MAX Specifications: Attenuator Type: Fixed ; Insertion Loss: 20 dB ; Attenuation: 1 dB AT-ST-A-M6-03-C : RF/MICROWAVE FIXED ATTENUATOR, 20 dB INSERTION LOSS-MAX Specifications: Attenuator Type: Fixed ; Insertion Loss: 20 dB ; Attenuation: 1 dB K4H560838F-ULB00 : 32M X 8 DDR DRAM, 0.75 ns, PBGA60 Specifications: Memory Category: DRAM Chip ; Density: 268435 kbits ; Number of Words: 32000 k ; Bits per Word: 8 bits ; Package Type: FBGA-60 ; Pins: 60 ; Logic Family: CMOS ; Supply Voltage: 2.5V ; Access Time: 0.7500 ns ; Operating Temperature: 0 to 70 C (32 to 158 F) K4H561638F-TCA2 : 16M X 16 DDR DRAM, 0.75 ns, PBGA60 Specifications: Memory Category: DRAM Chip ; Density: 268435 kbits ; Number of Words: 16000 k ; Bits per Word: 16 bits ; Package Type: FBGA-60 ; Pins: 60 ; Logic Family: CMOS ; Supply Voltage: 2.5V ; Access Time: 0.7500 ns ; Operating Temperature: 0 to 70 C (32 to 158 F) |