Details, datasheet, quote on part number: K4E640412E-JP50
| Part | K4E640412E-JP50 |
| Category | |
| Description | 8M x 8bit CMOS Dynamic RAM with Extended Data Out |
| Company | Samsung Semiconductor, Inc. |
| Datasheet | Download K4E640412E-JP50 Datasheet |
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| Quote |
| Features, Applications |
DESCRIPTION This is a family x 8 bit Extended Data Out Mode CMOS DRAMs. Extended Data Out Mode offers high speed random access of memory cells within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time or -60), power consumption( Normal or Low power) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This 8Mx8 EDO Mode DRAM family is fabricate d using Samsung s advanced CMOS process to realize high band-width, low power consumption and high reliability. FEATURESPart Identification K4E660812E-JC/L(3.3V, 8K Ref.) K4E640812E-JC/L(3.3V, 4K Ref.) K4E660812E-TC/L(3.3V, 8K Ref.) K4E640812E-TC/L(3.3V, 4K Ref.) Extended Data Out Mode operation CAS-before-RAS refresh capability RAS-only and Hidden refresh capability Self-refresh capability (L-ver only) Fast parallel test mode capability LVTTL(3.3V) compatible inputs and outputs Active Power Dissipation Unit : mW Speed -50 -60 Refresh Cycles Part NO. K4E660812E* K4E640812E Refresh cycle 8K 4K Refresh time Normal 64ms L-ver 128ms Early Write or output enable controlled write JEDEC Standard pinout Available in Plastic SOJ and TSOP(II) packages +3.3V �0.3V power supply 396 360 Refresh Control Refresh Counter Memory Array x 8 Cells* Access mode & RAS only refresh mode 8K cycle/128ms(L-ver.) CAS -before-RAS & Hidden refresh mode 4K cycle/128ms(L-ver.) Row Address Buffer Col. Address Buffer Column DecoderSAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. Pin Function Address Inputs(8K Product) Address Inputs(4K Product) Data In/Out Ground Row Address Strobe Column Address Strobe Read/Write Input Data Output Enable Power(+3.3V) No Connection Parameter Voltage on any pin relative to VSS Voltage VC C supply relative to VSS Storage Temperature Power Dissipation Short Circuit Output Current Symbol VIN, V CC Tstg PD IOS Address Rating 1 50 * Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS (Voltage referenced to Vss, to 70 �C)Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Symbol VC C VSS V IL Min Typ 3.3 0 Max Vcc+0.3 0.8 Vcc+1.3V at pulse width 15ns which is measured -1.3 at pulse width 15ns which is measured V SSDC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted.) Parameter Input Leakage Current (Any input NV CC+0.3V, all other pins not under test=0 Volt) Output Leakage Current (Data out is disabled, 0VV OUT VCC ) Output High Voltage Level(IO H=-2mA) Output Low Voltage Level(I OL =2mA) Symbol II(L) Min -5 Max 5 Units uA |
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