K4D553238F-GC2A datasheet - 256mbit GDDR Sdram

Details, datasheet, quote on part number: K4D553238F-GC2A
PartK4D553238F-GC2A
Category
Description256mbit GDDR Sdram
CompanySamsung Semiconductor, Inc.
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Features, Applications

x 4 Banks Graphic Double Data Rate Synchronous DRAM with Bi-directional Data Strobe and DLL (144-Ball FBGA)

Samsung Electronics reserves the right to change products or specification without notice.

x 4 Banks Graphic Double Data Rate Synchronous DRAM with Bi-directional Data Strobe and DLL FEATURES

+ 5% power supply for device operation + 5% power supply for I/O interface SSTL_2 compatible inputs/outputs 4 banks operation MRS cycle with address key programs Read latency 3, 4 (clock) Burst length (2, 4 and 8) Burst type (sequential & interleave) All inputs except data & DM are sampled at the positive going edge of the system clock Differential clock input No Wrtie-Interrupted by Read Function 4 DQS's 1DQS / Byte Data I/O transactions on both edges of Data strobe DLL aligns DQ and DQS transitions with Clock transition Edge aligned data & data strobe output Center aligned data & data strobe input DM for write masking only Auto & Self refresh 32ms refresh period (4K cycle) 144-Ball FBGA Maximum clock frequency to 350MHz Maximum data rate to 700Mbps/pin

Part NO. K4D553238F-JC40 K4D553238F-JC50 Max Freq. 250MHz 200MHz Max Data Rate SSTL_2 144-Ball FBGA Interface Package

K4D553238F-EC is the Lead Free package part number 2. For the K4D553238F-JC2A, VDD & VDDQ + 0.1V

The is 268,435,456 bits of hyper synchronous data rate Dynamic RAM organized x 2,097,152 words by 32 bits, fabricated with SAMSUNG's high performance CMOS technology. Synchronous features with Data Strobe allow extremely high performance to 2.8GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety of high performance memory system applications.


 

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