IZ1621

RAM Mapping 32x4 LCD Controller for I/O µC TECHNICAL DATA IZ1621 The IZ1621 is a 128 pattern (32x4), memory mapping, and multi-function LCD driver. The S/W configuration feature of the IZ1621 makes it suitable for multiple LCD applications including LCD modules and display subsystems. Only three or four lines are required for the interface betwee

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n the host controller and the HT1621. The IZ1621 contains a power down command to reduce power consumption. FEATURES • Operating voltage : 2.4V~5.2V • Built-in 256kHz RC oscillator • External 32.768kHz crystal or 256kHz frequency source input • Selection of 1/2 or 1/3 bias, and selection of 1/2 or 1/3 or 1/4 duty LCD applications • Internal time base frequency sources • Two selectable buzzer frequencies (2kHz/4kHz) • Power down command reduces power consumption • Built-in time base generator and WDT • Time base or WDT overflow output BLOCK DIAGRAM • 8 kinds of time base/WDT clock sources • 32x4 LCD driver • Built-in 32x4 bit display RAM • 3-wire serial interface • Internal LCD driving frequency source • Software configuration feature • Data mode and command mode instructions • R/W address auto increment • Three data accessing modes • VLCD pin for adjusting LCD operating voltage Note: CS: Chip selection BZ, BZ: Tone outputs WR, RD, DATA: Serial interface COM0~COM3, SEG0~SEG31: LCD outputs IRQ: Time base or WDT overflow output 1 IZ1621 Pad Location Pad Pad Name I/O Function No. Chip selection input with pull-high resistor 1 CS I When the CS is logic high, the data and command read from or written to the IZ1621 are disabled. The serial interface circuit is also reset. But if CS is at logic low level and is input to the CS pad, the data and command transmission between the host controller and the IZ1621 are all enabled. READ clock input with pull-high resistor 2 RD I Data in the RAM of the IZ1621 are clocked out on the falling edge of the RD signal. The clocked out data will appear on the DATA line. The host controller can use the next rising edge to latch the clocked out data. WRITE clock input with pull-high resistor 3 WR I Data on the DATA line are latched into the IZ1621 on the rising edge of the WR signal. 4 DATA I/O Serial data input/output with pull-high resistor 5 VSS - Negative power supply, ground 6 OSCO O The OSCO and OSCI pads are connected to a 32.768kHz crystal in order to generate a system clock. If the system clock comes from an external clock source, 7 OSCI I the external clock source should be connected to the OSCI pad. But if an on-chip RC oscillator is selected instead, the OSCO and OSCI pads can be left open. 8 VLCD I LCD power input 9 VDD - Positive power supply 10 IRQ O Time base or WDT overflow flag, NMOS open drain output 11, 12 BZ, BZ O 2kHz or 4kHz tone frequency output pair 13÷16 COM0÷COM