TTL compatible inputs and outputs; tristate I/O Refresh Interval: cycles/16 ms Refresh Mode: RAS-Only, CAS-before-RAS (CBR), Hidden JEDEC standard pinout Single power supply: 10% (IC41LV16105) Byte Write and Byte Read operation via two CAS Industrail temperature range to 85oC

16-bit high-performance CMOS Dynamic Random Access Memories.ast Page Mode allows 1,024 random accesses within a single row with access cycle time as short 20 ns per 16-bit word. The Byte Write control, of upper and lower byte, makes the IC41C16105 ideal for use 16-, 32-bit wide data bus systems. These features make the IC41C16105 and IC41LV16105 ideally suited for high-bandwidth graphics, digital signal processing, high-performance computing systems, and peripheral applications. The IC41C16105 and IC41LV16105 are packaged 42-pin 400mil SOJ and 44- (50-) pin TSOP-2.

Max. RAS Access Time (tRAC) Max. CAS Access Time (tCAC) Max. Column Address Access Time (tAA) Min.ast Page Mode Cycle Time (tPC) Min. Read/Write Cycle Time (tRC) Unit ns

WE OE RAS UCAS LCAS Vcc GND NC Address Inputs Data Inputs/Outputs Write Enable Output Enable Row Address Strobe Upper Column Address Strobe Lower Column Address Strobe Power Ground No Connection

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.unction Standby Read: Word Read: Lower Byte Read: Upper Byte Write: Word (Early Write) Write: Lower Byte (Early Write) Write: Upper Byte (Early Write) Read-Write(1,2) Hidden Refresh RAS-Only Refresh CBR Refresh(4) RAS LHL L HL LCAS UCAS OE LH Address tR/tC X ROW/COL ROW/NA X I/O High-Z DOUT Lower Byte, DOUT Upper Byte, High-Z Lower Byte, High-Z Upper Byte, DOUT DIN Lower Byte, DIN Upper Byte, High-Z Lower Byte, High-Z Upper Byte, DIN DOUT, DIN DOUT High-Z

Notes: 1. These WRITE cycles may also be BYTE WRITE cycles (either LCAS or UCAS active). 2. These READ cycles may also be BYTE READ cycles (either LCAS or UCAS active). 3. EARLY WRITE only. 4. At least one of the two CAS signals must be active (LCAS or UCAS).