Integrated Circuit Solution Inc. 1
DR026-0A 09/04/2001
IC41C44002A/IC41C44002AS(L)
IC41LV44002A/IC41LV44002AS(L)
Document Title
4Mx4 bit Dynamic RAM with EDO Page Mode
Revision History
Revision No History Draft Date Remark
0A Initial Draft September 4,2001
The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and
products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
2Integrated Circuit Solution Inc.
DR026-0A 09/04/2001
IC41C44002A/IC41C44002AS(L)
IC41LV44002A/IC41LV44002AS(L)
FEATURES
• Extended Data-Out (EDO) Page Mode
access cycle
• TTL compatible inputs and outputs
• Refresh Interval:
-- 2,048 cycles/32 ms
• Refresh Mode: RAS-Only,
CAS-before-RAS (CBR), and Hidden
• JEDEC standard pinout
• Single power supply:
5V ± 10% or 3.3V ± 10%
• Self Refresh 2048 cycles for S version
• Low power for L version.
DESCRIPTION
The ICSI 44002 Series is a 4,194,304 x 4-bit high-performance
CMOS Dynamic Random Access Memory. These devices
offer an accelerated cycle access called EDO Page Mode.
EDO Page Mode allows 2,048 random accesses within a single
row with access cycle time as short as 20 ns per 4-bit word.
These features make the 44002 Series ideally suited for high-
bandwidth graphics, digital signal processing, high-performance
computing systems, and peripheral applications.
The 44002 Series is packaged in a 24-pin 300mil SOJ and a 24
pin TSOP-2
4M x 4 (16-MBIT) DYNAMIC RAM
WITH EDO PAGE MODE
KEY TIMING PARAMETERS
Parameter -50 -60 Unit
RAS Access Time (tRAC)5060ns
CAS Access Time (tCAC)1315ns
Column Address Access Time (tAA)2530ns
EDO Page Mode Cycle Time (tPC)2025ns
Read/Write Cycle Time (tRC) 84 104 ns
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
PRODUCT SERIES OVERVIEW
Part No. Refresh Voltage
IS41C44002A 2K 5V ± 10%
IS41C44002AS(L) 2K 5V ± 10%
IS41LV44002A 2K 3.3V ± 10%
IS41LV44002AS(L) 2K 3.3V ± 10%
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VCC
I/O0
I/O1
WE
RAS
NC
A10
A0
A1
A2
A3
VCC
GND
I/O3
I/O2
CAS
OE
A9
A8
A7
A6
A5
A4
GND
PIN DESCRIPTIONS
A0-A10 Address Inputs (2K Refresh)
I/O0-3 Data Inputs/Outputs
WE Write Enable
OE Output Enable
RAS Row Address Strobe
CAS Column Address Strobe
Vcc Power
GND Ground
N C No Connection
PIN CONFIGURATION
24 Pin SOJ, TSOP-2
Integrated Circuit Solution Inc. 3
DR026-0A 09/04/2001
IC41C44002A/IC41C44002AS(L)
IC41LV44002A/IC41LV44002AS(L)
FUNCTIONAL BLOCK DIAGRAM
OE
WE
CAS CAS WE
OE
DATA I/O BUS
COLUMN DECODERS
SENSE AMPLIFIERS
MEMORY ARRAY
4,194,304 x 4
ROW DECODER
DATA I/O BUFFERS
CAS
CONTROL
LOGIC
WE
CONTROL
LOGICS
OE
CONTROL
LOGIC
I/O0-I/O3
RAS
RAS
A0-A10
RAS
CLOCK
GENERATOR
REFRESH
COUNTER
ADDRESS
BUFFERS
TRUTH TABLE
Function RASRAS
RASRAS
RAS CASCAS
CASCAS
CAS WEWE
WEWE
WE OEOE
OEOE
OE Address tR/tCI/O
Standby H H X X X High-Z
Read L L H L ROW/COL DOUT
Write: Word (Early Write) L L L X ROW/COL DIN
Read-Write L L H→LL→H ROW/COL DOUT, DIN
EDO Page-Mode Read 1st Cycle: L H→L H L ROW/COL DOUT
2nd Cycle: L H→L H L NA/COL DOUT
EDO Page-Mode Write 1st Cycle: L H→L L X ROW/COL DIN
2nd Cycle: L H→L L X NA/COL DIN
EDO Page-Mode 1st Cycle: L H→LH→LL→H ROW/COL DOUT, DIN
Read-Write 2nd Cycle: L H→LH→LL→H NA/COL DOUT, DIN
Hidden Refresh Read L→H→L L H L ROW/COL DOUT
Write
(1)
L→H→L L L X ROW/COL DIN
RAS-Only Refresh L H X X ROW/NA High-Z
CBR Refresh H→L L H X X High-Z
Note:
1. EARLY WRITE only.
4Integrated Circuit Solution Inc.
DR026-0A 09/04/2001
IC41C44002A/IC41C44002AS(L)
IC41LV44002A/IC41LV44002AS(L)
Functional Description
The IC41C44002A and IC41LV44002A are CMOS DRAMs
optimized for high-speed bandwidth, low power
applications. During READ or WRITE cycles, each bit is
uniquely addressed through the 11 address bits. These are
entered 11 bits (A0-A10) at a time for the 2K refresh device
. The row address is latched by the Row Address Strobe
(RAS). The column address is latched by the Column
Address Strobe (CAS). RAS is used to latch the first 11 bits
and CAS is used to latch the latter 11 bits.
Memory Cycle
A memory cycle is initiated by bring RAS LOW and it is
terminated by returning both RAS and CAS HIGH. To
ensures proper device operation and data integrity any
memory cycle, once initiated, must not be ended or
aborted before the minimum tRAS time has expired. A new
cycle must not be initiated until the minimum precharge
time tRP, tCP has elapsed.
Read Cycle
A read cycle is initiated by the falling edge of CAS or OE,
whichever occurs last, while holding WE HIGH. The
column address must be held for a minimum time specified
by tAR. Data Out becomes valid only when tRAC, tAA, tCAC
and tOE are all satisfied. As a result, the access time is
dependent on the timing relationships between these
parameters.
Write Cycle
A write cycle is initiated by the falling edge of CAS and WE,
whichever occurs last. The input data must be valid at or
before the falling edge of CAS or WE, whichever occurs
last.
Refresh Cycle
To retain data, 2,048 refresh cycles are required in each
32 ms period. There are two ways to refresh the memory:
1. By clocking each of the 2,048 row addresses (A0
through A10) with RAS at least once every 32 ms. Any
read, write, read-modify-write or RAS-only cycle re-
freshes the addressed row.
2. Using a CAS-before-RAS refresh cycle. CAS-before-
RAS refresh is activated by the falling edge of RAS,
while holding CAS LOW. In CAS-before-RAS refresh
cycle, an internal 11-bit counter provides the row ad-
dresses and the external address inputs are ignored.
CAS-before-RAS is a refresh-only mode and no data
access or device selection is allowed. Thus, the output
remains in the High-Z state during the cycle.
Self Refresh Cycle(1)
The Self Refresh allows the user a dynamic refresh, data
retention mode at the extended refresh period of 64 ms. i.
e., 32 µs per row when using distributed CBR refreshes.
The feature also allows the user the choice of a fully static,
low power data retention mode. The optional Self Refresh
feature is initiated by performing a CBR Refresh cycle and
holding RAS LOW for the specified tRASS.
The Self Refresh mode is terminated by driving RAS HIGH
for a minimum time of tRPS. This delay allows for the
completion of any internal refresh cycles that may be in
process at the time of the RAS LOW-to-HIGH transition. If
the DRAM controller uses a distributed refresh sequence,
a burst refresh is not required upon exiting Self Refresh.
However, if the DRAM controller utilizes a RAS-only or
burst refresh sequence, all 2048 rows must be refreshed
within the average internal refresh rate, prior to the resump-
tion of normal operation.
Power-On
After application of the VCC supply, an initial pause of
200 µs is required followed by a minimum of eight initial-
ization cycles (any combination of cycles containing a
RAS signal).
During power-on, it is recommended that RAS track with
VCC or be held at a valid VIH to avoid current surges.
Note:
1.Self Refresh is for S version only.
Integrated Circuit Solution Inc. 5
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IC41C44002A/IC41C44002AS(L)
IC41LV44002A/IC41LV44002AS(L)
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameters Rating Unit
VTVoltage on Any Pin Relative to GND 5V −1.0 to +7.0 V
3.3V −0.5 to +4.6
VCC Supply Voltage 5V −1.0 to +7.0 V
3.3V −0.5 to +4.6
IOUT Output Current 50 mA
PDPower Dissipation 1 W
TACommercial Operation Temperature 0 to +70 oC
TSTG Storage Temperature −55 to +125 oC
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
RECOMMENDED OPERATING CONDITIONS (Voltages are referenced to GND.)
Symbol Parameter Min. Typ. Max. Unit
VCC Supply Voltage 5V 4.5 5.0 5.5 V
3.3V 3.0 3.3 3.6
VIH Input High Voltage 5V 2.4 −VCC + 1.0 V
3.3V 2.0 −VCC + 0.3
VIL Input Low Voltage 5V −1.0 −0.8 V
3.3V −0.3 −0.8
TACommercial Ambient Temperature 0 −70 oC
CAPACITANCE(1,2)
Symbol Parameter Max. Unit
CIN1Input Capacitance: A0-A10(A11) 5 pF
CIN2Input Capacitance: RAS, CAS, WE, OE 7pF
CIO Data Input/Output Capacitance: I/O0-I/O3 7 pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25oC, f = 1 MHz.
6Integrated Circuit Solution Inc.
DR026-0A 09/04/2001
IC41C44002A/IC41C44002AS(L)
IC41LV44002A/IC41LV44002AS(L)
ELECTRICAL CHARACTERISTICS(1)
(Recommended Operating Conditions unless otherwise noted.)
Symbol Parameter Test Condition Speed Min. Max. Unit
IIL Input Leakage Current Any input 0V ≤ VIN ≤ Vcc −55µA
Other inputs not under test = 0V
IIO Output Leakage Current Output is disabled (Hi-Z) −55µA
0V ≤ VOUT ≤ Vcc
VOH Output High Voltage Level IOH = −5.0 mA with VCC=5V 2.4 −V
IOH = −2.0 mA with VCC=3.3V
VOL Output Low Voltage Level IOL = 4.2 mA with VCC=5V −0.4 V
IOL = 2 mA with VCC=3.3V
ICC1Standby Current: TTL RAS, CAS ≥ VIH 5V −2mA
3.3V −2
ICC2Standby Current: CMOS RAS, CAS ≥ VCC − 0.2V 5V −1mA
3.3V −0.5
ICC3Operating Current: RAS, CAS, -50 −120 mA
Random Read/Write(2,3,4) Address Cycling, tRC = tRC (min.) -6 0 −110
Average Power Supply Current
ICC4Operating Current: RAS = VIL, CAS, -50 −90 mA
EDO Page Mode(2,3,4) Cycling tPC = tPC (min.) -60 −80
Average Power Supply Current
ICC5Refresh Current: RAS, CAS Cycling -5 0 −120 mA
CBR(2,3,5) tRC = tRC (min.) - 6 0 −110
Average Power Supply Current
ICCSSelf Refresh current(6) Self Refresh Mode 5V,nromal version 5 0 0 µA
5V, L version 350
3.3V, normal version 45 0
3.3, L version 350
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.
2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.
4. Column-address is changed once each EDO page cycle.
5. Enables on-chip refresh and address counters.
6. ICCS is for S version only.
Integrated Circuit Solution Inc. 7
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IC41C44002A/IC41C44002AS(L)
IC41LV44002A/IC41LV44002AS(L)
AC CHARACTERISTICS(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.)
-50 -60
Symbol Parameter Min. Max. Min. Max. Units
tRC Random READ or WRITE Cycle Time 84 −104 −ns
tRAC Access Time from RAS(6, 7) −50 −60 ns
tCAC Access Time from CAS(6, 8, 15) −14 −15 ns
tAA Access Time from Column-Address(6) −25 −30 ns
tRAS RAS Pulse Width 50 10 K 60 10 K ns
tRP RAS Precharge Time 3 0 −40 −ns
tCAS CAS Pulse Width(23) 8 10K 10 10K ns
tCP CAS Precharge Time(9) 10 −10 −ns
tCSH CAS Hold Time (21) 38 −40 −ns
tRCD RAS to CAS Delay Time(10, 20) 12 37 14 45 ns
tASR Row-Address Setup Time 0 −0−ns
tRAH Row-Address Hold Time 8 −10 −ns
tASC Column-Address Setup Time(20) 0−0−ns
tCAH Column-Address Hold Time(20) 8−10 −ns
tRAD RAS to Column-Address Delay Time(11) 10 25 12 30 ns
tRAL Column-Address to RAS Lead Time 2 5 −30 −ns
tRSH RAS Hold Time 8 −10 −ns
tRHCP RAS Hold Time from CAS Precharge 3 0 −35 −ns
tCLZ CAS to Output in Low-Z(15, 24) 0−0−ns
tCRP CAS to RAS Precharge Time(21) 5−5−ns
tOD Output Disable Time(19, 24) 015 015 ns
tOE Output Enable Time(15, 16) −12 −15 ns
tOED Output Enable Data Delay (Write) 2 0 −20 −ns
tOEHC OE HIGH Hold Time from CAS HIGH 5 −5−ns
tOEP OE HIGH Pulse Width 1 0 −10 −ns
tRCS Read Command Setup Time(17, 20) 0−0−ns
tRRH Read Command Hold Time 0 −0−ns
(referenced to RAS)(12)
tRCH Read Command Hold Time 0 −0−ns
(referenced to CAS)(12, 17, 21)
tWCH Write Command Hold Time(17) 8−10 −ns
tWP Write Command Pulse Width(17) 8−10 −ns
tWPZ WE Pulse Widths to Disable Outputs 10 −10 −ns
tRWL Write Command to RAS Lead Time(17) 13 −15 −ns
tCWL Write Command to CAS Lead Time(17, 21) 8−10 −ns
tWCS Write Command Setup Time(14, 17, 20) 0−0−ns
8Integrated Circuit Solution Inc.
DR026-0A 09/04/2001
IC41C44002A/IC41C44002AS(L)
IC41LV44002A/IC41LV44002AS(L)
AC CHARACTERISTICS (Continued)(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.)
-50 -60
Symbol Parameter Min. Max. Min. Max. Units
tOEH OE Hold Time from WE during 8 −10 −ns
READ-MODIFY-WRITE cycle(18)
tDS Data-In Setup Time(15, 22) 0−0−ns
tDH Data-In Hold Time(15, 22) 8−10 −ns
tRWC READ-MODIFY-WRITE Cycle Time 1 08 −133 −ns
tRWD RAS to WE Delay Time during 6 4 −77 −ns
READ-MODIFY-WRITE Cycle(14)
tCWD CAS to WE Delay Time(14, 20) 26 −32 −ns
tAWD Column-Address to WE Delay Time(14) 39 −47 −ns
tPC EDO Page Mode READ or WRITE 2 0 −25 −ns
Cycle Time
tRASP RAS Pulse Width in EDO Page Mode 50 100K 60 100K ns
tCPA Access Time from CAS Precharge(15) −30 −35 ns
tPRWC EDO Page Mode READ-WRITE 5 6 −68 −ns
Cycle Time
tCOH Data Output Hold after CAS LOW 5 −5−ns
tOFF Output Buffer Turn-Off Delay from 0 1 2 0 1 5 ns
CAS or RAS(13,15,19, 24)
tWHZ Output Disable Delay from WE 310 310 ns
tCSR CAS Setup Time (CBR REFRESH)(20, 25) 5−5−ns
tCHR CAS Hold Time (CBR REFRESH)( 21, 25) 8−10 −ns
tRPC RAS to CAS Precharge Time 5 −5−ns
tORD OE Setup Time prior to RAS during 0 −0−ns
HIDDEN REFRESH Cycle
tREF Auto Refresh Period 2,048 Cycles −32 −32 ms
tTTransition Time (Rise or Fall)(2, 3) 1501 50ns
AC TEST CONDITIONS
Output load: Two TTL Loads and 100 pF (Vcc=5.0V±10%)
One TTL Loads and 100 pF (Vcc=3.3V±10%)
Input timing reference levels: VIH = 2.4V, VIL = 0.8V
Output timing reference levels: VOH = 2.0V, VOL = 0.8V
Integrated Circuit Solution Inc. 9
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IC41C44002A/IC41C44002AS(L)
IC41LV44002A/IC41LV44002AS(L)
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycle (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.
2. VIH (MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times, are measured between VIH
and VIL (or between VIL and VIH) and assume to be 1 ns for all inputs.
3. In addition to meeting the transition rate specification, all input signals must transit between VIH and VIL (or between VIL and VIH)
in a monotonic manner.
4. If CAS and RAS = VIH, data output is High-Z.
5. If CAS = VIL, data output may contain data from the last valid READ cycle.
6. Measured with a load equivalent to one TTL gate and 50 pF.
7. Assumes that ≤ tRCD After appli tRCD (MAX). If tRCD is greater than the maximum recommended value shown in this table, tRAC will
increase by the amount that tRCD exceeds the value shown.
8. Assumes that tRCD ≥ tRCD (MAX).
9. If CAS is LOW at the falling edge of RAS, data out will be maintained from the previous cycle. To initiate a new cycle and clear the
data output buffer, CAS and RAS must be pulsed for tCP.
10. Operation with the tRCD (MAX) limit ensures that tRAC (MAX) can be met. tRCD (MAX) is specified as a reference point only; if tRCD
is greater than the specified tRCD (MAX) limit, access time is controlled exclusively by tCAC.
11. Operation within the tRAD (MAX) limit ensures that tRCD (MAX) can be met. tRAD (MAX) is specified as a reference point only; if tRAD
is greater than the specified tRAD (MAX) limit, access time is controlled exclusively by tAA.
12. Either tRCH or tRRH must be satisfied for a READ cycle.
13. tOFF (MAX) defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL.
14. tWCS, tRWD, tAWD and tCWD are restrictive operating parameters in LATE WRITE and READ-MODIFY-WRITE cycle only. If tWCS ≥ tWCS
(MIN), the cycle is an EARLY WRITE cycle and the data output will remain open circuit throughout the entire cycle. If tRWD ≥ tRWD
(MIN), tAWD ≥ tAWD (MIN) and tCWD ≥ tCWD (MIN), the cycle is a READ-WRITE cycle and the data output will contain data read from
the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go back
to VIH) is indeterminate. OE held HIGH and WE taken LOW after CAS goes LOW result in a LATE WRITE (OE-controlled) cycle.
15. Output parameter (I/O) is referenced to corresponding CAS input.
16. During a READ cycle, if OE is LOW then taken HIGH before CAS goes HIGH, I/O goes open. If OE is tied permanently LOW, a
LATE WRITE or READ-MODIFY-WRITE is not possible.
17. Write command is defined as WE going low.
18. LATE WRITE and READ-MODIFY-WRITE cycles must have both tOD and tOEH met (OE HIGH during WRITE cycle) in order to ensure
that the output buffers will be open during the WRITE cycle. The I/Os will provide the previously written data if CAS remains LOW
and OE is taken back to LOW after tOEH is met.
19. The I/Os are in open during READ cycles once tOD or tOFF occur.
20. Determined by falling edge of CAS.
21. Determined by rising edge of CAS.
22. These parameters are referenced to CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or READ-
MODIFY-WRITE cycles.
23. CAS must meet minimum pulse width.
24. The 3 ns minimum is a parameter guaranteed by design.
25. Enables on-chip refresh and address counters.
10 Integrated Circuit Solution Inc.
DR026-0A 09/04/2001
IC41C44002A/IC41C44002AS(L)
IC41LV44002A/IC41LV44002AS(L)
READ CYCLE
Note:
1. tOFF is referenced from rising edge of RAS or CAS, whichever occurs last.
t
RAS
t
RC
t
RP
t
CAH
t
ASC
t
RAD
t
RAL
OE
I/O
WE
ADDRESS
CAS
RAS
Row Column Row
Open Open
Valid Data
t
CSH
t
CAS
t
RSH
t
CRP
t
RCD
t
RAH
t
ASR
t
RRH
t
RCH
t
RCS
t
AA
t
CAC
t
OFF(1)
t
RAC
t
CLZ
t
OE
t
OD
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IC41C44002A/IC41C44002AS(L)
IC41LV44002A/IC41LV44002AS(L)
EARLY WRITE CYCLE (OE = DON'T CARE)
t
RAS
t
RC
t
RP
t
CAH
t
ASC
t
RAD
t
RAL
I/O
WE
ADDRESS
CAS
RAS
Row Column Row
t
CSH
t
CAS
t
RSH
t
CRP
t
RCD
t
RAH
t
ASR
t
CWL
t
WCH
t
RWL
t
WP
t
WCS
t
DH
t
DS
Valid Data
12 Integrated Circuit Solution Inc.
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IC41C44002A/IC41C44002AS(L)
IC41LV44002A/IC41LV44002AS(L)
READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE Cycles)
tRAS
tRWC tRP
tCAH
tASC
tRAD tRAL
WE
OE
ADDRESS
CAS
RAS
Row Column Row
tCSH
tCAS
tRSH
tCRP tRCD
tRAHtASR
tRWD tCWL
tCWD tRWL
tAWD tWP
tRCS
tCAC
tCLZ tDS tDH
tOEHtOD
tOE
tRAC tAA
I/O Open Open
Valid DOUT Valid DIN
Integrated Circuit Solution Inc. 13
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IC41C44002A/IC41C44002AS(L)
IC41LV44002A/IC41LV44002AS(L)
EDO-PAGE-MODE READ CYCLE
Note:
1. tPC can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of CAS to rising edge of CAS. Both
measurements must meet the tPC specifications.
tRASP tRP
ADDRESS
CAS
RAS
Row Row
tCAS
tCRP tRCD
tCSH tCP tCAS
tCAH
tCAS
tRAL
tRSH tCPtCP
tPC
(1)
tASR
tRAH
tRAD
Column Column
tCAHtCAH
Column
tASCtASC
OE
I/O
WE
Open Open
Valid Data
tAA tAA
tCPA
tCAC tCAC
tRAC
tCOHtCLZ
tOEP
tOE tOD
tOEtOEHC
Valid Data
tRCH tRRH
tAA
tCPA
tCAC tOFFtCLZ
Valid Data
tOD
tASC
tRCS
14 Integrated Circuit Solution Inc.
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IC41C44002A/IC41C44002AS(L)
IC41LV44002A/IC41LV44002AS(L)
EDO-PAGE-MODE EARLY-WRITE CYCLE
tRASP tRP
ADDRESS
CAS
RAS
Row Row
tCAS
tCRP tRCD
tCSH tCP tCAS
tCAH
tCAS
tRAL
tRSH tCPtCP
tPC
tASR
tRAH
tRAD
Column Column
tCAHtCAH
Column
tASCtASC
OE
I/O
WE
Valid Data
tASC
tWCS
tWCH
tCWL
tWP
tWCS
tWCH
tCWL
tWP
tDS tDH
tWCS
tWCH
tCWL
tWP
Valid Data
tDS tDH
Valid Data
tDS
tRWL
tDH
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IC41C44002A/IC41C44002AS(L)
IC41LV44002A/IC41LV44002AS(L)
EDO-PAGE-MODE READ-WRITE CYCLE (LATE WRITE and READ-MODIFY WRITE Cycles)
Note:
1. tPC is for LATE WRITE only. tPC can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of CAS to
rising edge of CAS. Both measurements must meet the tPC specifications.
t
RASP
t
RP
ADDRESS
CAS
RAS
Row Row
t
CRP
t
RCD
t
CSH
t
CP
t
CAH
t
CAS
t
RAL
t
RSH
t
CP
t
CP
t
RAH
t
RAD
t
ASR
Column Column
t
CAH
t
CAH
Column
t
ASC
t
ASC
t
CAS
t
CAS
OE
I/O
WE
t
ASC
t
RWD
t
RCS
t
CWL
t
WP
t
AWD
t
CWD
t
DH
t
DS
t
CAC
t
CLZ
t
AWD
t
CWD
t
CWL
t
WP
t
AWD
t
CWD
t
CWL
t
RWL
t
WP
Open Open
DINDOUT
t
OE
t
OE
t
OE
t
OD
t
OEH
t
OD
t
OD
t
DH
t
DS
t
CPA
t
AA
t
CAC
t
CLZ
DINDOUT
t
DH
t
DS
t
CAC
t
CLZ
DINDOUT
t
CPA
t
AA
t
RAC
t
AA
t
PC
/ t
PRWC
(1)
16 Integrated Circuit Solution Inc.
DR026-0A 09/04/2001
IC41C44002A/IC41C44002AS(L)
IC41LV44002A/IC41LV44002AS(L)
EDO-PAGE-MODE READ-EARLY-WRITE CYCLE (Psuedo READ-MODIFY WRITE)
tRASP tRP
ADDRESS
CAS
RAS
Row Row
tCRP tRCD
tPC
tCSH
tCP
tCAH
tCAS
tRAL
tRSH tCPtCP
tRAH
tRAD
tASR
Column (A) Column (N)
tCAHtCAH
Column (B)
tASCtASC
tCAS tCAS
OE
I/O
WE
tASC
tCAC
tRCH
tDH
Open Open
Valid Data (A)
tOE
tWCS
tCAC
tCOH
DIN
tCPA
tWCH
tRAC tAA
tPC
Valid Data (B)
tWHZ
tDS
tRCS
tAA
Integrated Circuit Solution Inc. 17
DR026-0A 09/04/2001
IC41C44002A/IC41C44002AS(L)
IC41LV44002A/IC41LV44002AS(L)
AC WAVEFORMS
READ CYCLE (With WE-Controlled Disable)
RASRAS
RASRAS
RAS-ONLY REFRESH CYCLE (OE, WE = DON'T CARE)
t
CAH
t
ASC
t
ASC
t
RAD
OE
I/O
WE
ADDRESS
CAS
RAS
Row Column
Open Open
Valid Data
t
CSH
t
CAS
t
CRP
t
RCD
t
CP
t
RAH
t
ASR
t
RCH
t
RCS
t
RCS
t
AA
t
CAC
t
WHZ
t
RAC
t
CLZ
t
CLZ
t
OE
t
OD
Column
tRAS tRC tRP
I/O
ADDRESS
CAS
RAS
Row Row
Open
tCRP
tRAHtASR
tRPC
18 Integrated Circuit Solution Inc.
DR026-0A 09/04/2001
IC41C44002A/IC41C44002AS(L)
IC41LV44002A/IC41LV44002AS(L)
HIDDEN REFRESH CYCLE(1) (WE = HIGH; OE = LOW)
CBR REFRESH CYCLE (Addresses; OE = DON'T CARE, WE=HIGH)
Notes:
1. A Hidden Refresh may also be performed after a Write Cycle. In this case, WE = LOW and OE = HIGH.
2. tOFF is referenced from rising edge of RAS or CAS, whichever occurs last.
t
RAS
t
RAS
t
RP
t
RP
I/O
CAS
RAS
Open
t
CP
t
RPC
t
CSR
t
CHR
t
RPC
t
CSR
t
CHR
t
RAS
t
RAS
t
RP
CAS
RAS
t
CRP
t
RCD
t
RSH
t
CHR
t
ASC
t
RAD
ADDRESS Row Column
t
RAH
t
ASR
t
RAL
t
CAH
I/O Open Open
Valid Data
t
AA
t
CAC
t
RAC
t
CLZ
t
OFF
(2)
OE
t
OE
t
ORD
t
OD
Integrated Circuit Solution Inc. 19
DR026-0A 09/04/2001
IC41C44002A/IC41C44002AS(L)
IC41LV44002A/IC41LV44002AS(L)
SELF REFRESH CYCLE (Addresses : WE and OE = DON'T CARE)
t
RASS
t
RP
t
RPS
DQ
CAS
RAS
Open
t
CP
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
t
RPC
t
CSR
t
CHD
t
RPC
t
CP
TIMING PARAMETERS
-50 -60
Symbol Min. Max. Min. Max. Units
tCHD 10 — 10 — ns
tCP 9— 9— ns
tCSR 10 — 10 — ns
tRASS 100 — 100 — µs
tRP 30 — 40 — ns
tRPS 84 — 104 — ns
tRPC 5— 5— ns
20 Integrated Circuit Solution Inc.
DR026-0A 09/04/2001
IC41C44002A/IC41C44002AS(L)
IC41LV44002A/IC41LV44002AS(L)
Integrated Circuit Solution Inc.
HEADQUARTER:
NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK,
HSIN-CHU, TAIWAN, R.O.C.
TEL: 886-3-5780333
Fax: 886-3-5783000
BRANCH OFFICE:
7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD,
HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C.
TEL: 886-2-26962140
FAX: 886-2-26962252
http://www.icsi.com.tw
ORDERING INFORMATION
Commercial Range: 0°°
°°
°C to 70°°
°°
°C
Voltage: 5V
Speed (ns) Order Part No. Refresh Package
50 IC41C44002A-50J 2K 300mil SOJ
50 IC41C44002A-50T 2K 300mil TSOP-2
60 IC41C44002A-60J 2K 300-mil SOJ
60 IC41C44002A-60T 2K 300mil TSOP-2
Speed (ns) Order Part No. Refresh Package
50 IC41C44002AS-50J 2K 300mil SOJ
50 IC41C44002AS-50T 2K 300mil TSOP-2
50 IC41C44002ASL-50J 2K 300mil SOJ
50 IC41C44002ASL-50T 2K 300mil TSOP-2
60 IC41C44002AS-60J 2K 300mil SOJ
60 IC41C44002AS-60T 2K 300mil TSOP-2
60 IC41C44002ASL-60J 2K 300mil SOJ
60 IC41C44002ASL-60T 2K 300mil TSOP-2
Voltage: 3.3V
Speed (ns) Order Part No. Refresh Package
50 IC41LV44002A-50J 2K 300mil SOJ
50 IC41LV44002A-50T 2K 300mil TSOP-2
60 IC41LV44002A-60J 2K 300mil SOJ
60 IC41LV44002A-60T 2K 300mil TSOP-2
Speed (ns) Order Part No. Refresh Package
50 IC41LV44002AS-50J 2K 300mil SOJ
50 IC41LV44002AS-50T 2K 300mil TSOP-2
50 IC41LV44002ASL-50J 2K 300mil SOJ
50 IC41LV44002ASL-50T 2K 300mil TSOP-2
60 IC41LV44002AS-60J 2K 300mil SOJ
60 IC41LV44002AS-60T 2K 300mil TSOP-2
60 IC41LV44002ASL-60J 2K 300mil SOJ
60 IC41LV44002ASL-60T 2K 300mil TSOP-2