x 18 organizations x 18 organizations 0.25 Micron CMOS technology Synchronous Pipeline Mode of Operation with Self-Timed Late Write Single Differential HSTL Clock +2.5V Power Supply, Ground, 1.5, 1.8V VDDQ, and 0.90V VREF HSTL Input and Output levels Registered Addresses, Write Enables, Synchronous Select, and Data Ins

Registered Outputs Common I/O Asynchronous Output Enable Synchronous Power Down Input Boundary Scan using limited set of JTAG 1149.1 functions Byte Write Capability and Global Write Enable x 17 Bump Ball Grid Array Package with SRAM JEDEC Standard Pinout and Boundary SCAN Order

The 4Mb and IBM0418A41BLAB, IBM0418A81BLAB, and IBM0436A81BLAB--are Synchronous Pipeline Mode, high-performance CMOS Static Random Access Memories that are versatile, wide I/O, and can achieve 3ns cycle times. Differential K clocks are used to initiate the read/write operation and all internal operations are self-timed. At the rising edge of the K clock, all Addresses, Write-Enables, Sync Select, and Data Ins are registered internally. Data Outs are updated from output registers off the next rising edge of the K clock. An internal Write buffer allows write data to follow one cycle after addresses and controls. The device is operated with a single +2.5V power supply and is compatible with HSTL I/O interfaces.

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VDDQ DQ23 DQ20 VDDQ DQ18 DQ25 VDDQ DQ34 DQ32 VDDQ DQ27 NC VDDQ DQ24 DQ21 VDD SA NC TMS 3 SA VSS SBWc VSS VREF VSS SBWd VSS M1* SA TDI 4 NC VDD G NC VDD SA0 SA1 VDD SA TCK 5 SA VSS SBWb VSS VREF VSS SBWa VSS M2* SA TDO 6 SA NC, DQ15 DQ17 VDD NC 7 VDDQ DQb9 DQb11 VDDQ DQb14 DQb16 VDDQ DQ7 DQ5 VDDQ NC ZZ VDDQ

Note: * M1 and M2 are clock mode pins. For this application, M1 and M2 need to connect to VSS and VDD, respectively.

VDDQ DQ9 NC VDDQ NC DQ12 VDDQ NC DQ13 VDDQ DQ14 NC VDDQ DQ16 NC VDD DQ10 SA TMS 3 SA VSS SBWb VSS VREF VSS NC VSS M1 SA TDI 4 NC VDD G NC VDD SA0 SA1 VDD NC TCK 5 SA VSS NC VSS VREF VSS SBWa VSS M2 SA TDO 6 SA NC, NC DQ2 VDD NC 7 VDDQ NC DQ4 VDDQ DQ8 NC VDDQ DQ3 NC VDDQ NC ZZ VDDQ

Note: * M1 and M2 are clock mode pins. For this application, M1 and M2 need to connect to VSS and VDD respectively.

Address Input SA0-SA18 for 18 SA0-SA17 for 36 SA0-SA17 for 18 SA0-SA16 for x 36 Data I/O DQ0-DQ17 for 18 DQ0-DQ35 for x 36 Differential Input Register Clocks Write Enable, Global Write Enable, Byte a (DQ0-DQ8) Write Enable, Byte b (DQ9-DQ17) Write Enable, Byte c (DQ18-DQ26) Write Enable, Byte d (DQ27-DQ35) IEEE 1149.1 Test Inputs (LVTTL levels) IEEE 1149.1 Test Output (LVTTL level)

Clock Mode Inputs - Selects Single or Dual Clock Operation. HSTL Input Reference Voltage Power Supply (+2.5V) Ground Output Power Supply Synchronous Sleep Mode Output Driver Impedance Control No Connect

Part Number IBM0436A81BLAB -5 Organization x 36 Speed 1.7ns Access / 3.0ns Cycle 1.8ns Access / 3.3ns Cycle 1.8ns Access / 3.7ns Cycle 2.0ns Access / 4.0ns Cycle 2.25ns Access /5.0ns Cycle 1.7ns Access / 3.0ns Cycle 2.0ns Access / 3.3ns Cycle 1.8ns Access / 3.7ns Cycle 2.0ns Access / 4.0ns Cycle 2.25ns Access /5.0ns Cycle 1.7ns Access / 3.0ns Cycle 1.8ns Access / 3.3ns Cycle 1.8ns Access / 3.7ns Cycle 2.0ns Access / 4.0ns Cycle 2.25ns Access /5.0ns Cycle 1.7ns Access / 3.0ns Cycle 1.8ns Access / 3.3ns Cycle 1.8ns Access / 3.7ns Cycle 2.0ns Access / 4.0ns Cycle 2.25ns Access /5.0ns Cycle Leads x 17 BGA x 17 BGA x 17 BGA x 17 BGA x 17 BGA x 17 BGA x 17 BGA x 17 BGA x 17 BGA x 17 BGA x 17 BGA x 17 BGA x 17 BGA x 17 BGA x 17 BGA x 17 BGA x 17 BGA x 17 BGA x 17 BGA x 17 BGA