x 18 organizations x 18 organizations 0.25 Micron CMOS technology Synchronous Pipeline Mode of Operation with Self-Timed Late Write Single Differential HSTL Clock +2.5V Power Supply, Ground, 1.6V VDDQ, and 0.95V VREF HSTL Input and Output levels Registered Addresses, Write Enables, Synchronous Select, and Data Ins

Registered Outputs Common I/O Asynchronous Output Enable and Power Down Inputs Boundary Scan using limited set of JTAG 1149.1 functions Byte Write Capability and Global Write Enable x 17 Bump Ball Grid Array Package with SRAM JEDEC Standard Pinout and Boundary SCAN Order Programmable Impedance Output Drivers

The 4Mb and IBM0418A41XLAB, IBM0418A81XLAB, and IBM0436A81XLAB--are Synchronous Pipeline Mode, high-performance CMOS Static Random Access Memories that are versatile, have wide I/O, and can achieve 3ns cycle times. Differential K clocks are used to initiate the read/write operation and all internal operations are self-timed. At the rising edge of the K clock, all Addresses, WriteEnables, Sync Select, and Data Ins are registered internally. Data Outs are updated from output registers off the next rising edge of the K clock. An internal Write buffer allows write data to follow one cycle after addresses and controls. The chip is operated with a single +2.5V power supply and is compatible with HSTL I/O interfaces.

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VDDQ DQ19 DQ22 VDDQ DQ24 DQ25 VDDQ DQ34 DQ33 VDDQ DQ28 NC VDDQ DQ23 DQ26 VDD 3 SA VSS SBWc VSS VREF VSS SBWd VSS 4 NC VDD G NC VDD SW SA VDD 5 SA VSS SBWb VSS VREF VSS SBWa VSS DQ14 DQ17 VDD NC 7 VDDQ DQ10 DQb13 VDDQ DQb15 DQb16 VDDQ DQ7 DQ6 VDDQ NC ZZ

VDDQ TMS TDI TCK TDO NC Note: * M1 and M2 are clock mode pins. For this application, M1 and M2 need to connect to VSS and VDD, respectively.

VDDQ DQ14 NC VDDQ NC DQ17 VDDQ NC DQ12 VDDQ DQ11 NC VDDQ DQ16 NC VDD 3 SA VSS SBWb VSS VREF VSS NC VSS 4 NC VDD G NC VDD SW SA VDD 5 SA VSS NC VSS VREF VSS SBWa VSS NC DQ4 VDD SA 7 VDDQ NC DQ1 VDDQ DQ3 NC VDDQ DQ8 NC VDDQ NC ZZ VDDQ

TMS TDI TCK TDO NC Note: * M1 and M2 are clock mode pins. For this application, M1 and M2 need to connect to VSS and VDD respectively.

Address Input SA0-SA18 for 18 SA0-SA17 for 36 SA0-SA17 for 18 SA0-SA16 for x 36 Data I/O DQ0-DQ17 for 18 DQ0-DQ35 for x 36 Differential Input Register Clocks Write Enable, Global Write Enable, Byte a (DQ0-DQ8) Write Enable, Byte b (DQ9-DQ17) Write Enable, Byte c (DQ18-DQ26) Write Enable, Byte d (DQ27-DQ35) IEEE 1149.1 Test Inputs (LVTTL levels) IEEE 1149.1 Test Output (LVTTL level)

Clock Mode Inputs- Selects Single or Dual Clock Operation. HSTL Input Reference Voltage Power Supply (+2.5V) Ground Output Power Supply Synchronous Sleep Mode Output Driver Impedance Control No Connect

Part Number 36 2.0ns Access / 4.0ns Cycle 2.25ns Access /5.0ns Cycle 1.7ns Access / 3.0ns Cycle 2.0ns Access / 4.0ns Cycle 2.25ns Access /5.0ns Cycle 2.0ns Access / 4.0ns Cycle 2.25ns Access /5.0ns Cycle x 17 BGA 1.7ns Access / 3.0ns Cycle 1.7ns Access / 3.0ns Cycle x 18 Organization Speed 1.7ns Access / 3.0ns Cycle 2.0ns Access / 4.0ns Cycle 2.25ns Access /5.0ns Cycle 1.7ns Access / 3.0ns Cycle 1.7ns Access / 3.0ns Cycle Leads