HUF76629D3(S) by onsemi Datasheet | DigiKey

HUF76629D3(S) Datasheet by onsemi

FAIRCHILD SEMICONDUCTOR” mar " C W: W
©2001 Fairchild Semiconductor Corporation HUF76629D3, HUF76629D3S Rev. B
HUF76629D3, HUF76629D3S
20A, 100V, 0.054 Ohm, N-Channel, Logic
Level UltraFET® Power MOSFET
Packaging
Symbol
Features
Ultra Low On-Resistance
-r
DS(ON) = 0.052Ω, VGS = 10V
-r
DS(ON) = 0.054Ω, VGS = 5V
Simulation Models
- Temperature Compensated PSPICE® and SABER™
Electriecal Models
- Spice and SABER Thermal Impedance Models
- www.fairchildsemi.com
Peak Current vs Pulse Width Curve
UIS Rating Curve
Switching Time vs RGS Curves
Ordering Information
Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified
Product reliability information can be found at http://www.fairchildsemi.com/products/discrete/reliability/index.html
For severe environments, see our Automotive HUFA series.
All Fairchild semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification.
JEDEC TO-251AA JEDEC TO-252AA
DRAIN
(FLANGE)
DRAIN
SOURCE
GATE
HUF76629D3
GATE
SOURCE
DRAIN
(FLANGE
)
HUF76629D3S
D
G
S
PART NUMBER PACKAGE BRAND
HUF76629D3 TO-251AA 76629D
HUF76629D3S TO-252AA 76629D
NOTE: When ordering, use the entire part number. Add the suffix T
to obtain the variant in tape and reel, e.g., HUF76629D3ST.
HUF76629D3, HUF76629D3S UNITS
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS 100 V
Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR 100 V
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS ±16 V
Drain Current
Continuous (TC= 25oC, VGS = 5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Continuous (TC= 25oC, VGS = 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Continuous (TC= 100oC, VGS = 5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Continuous (TC= 100oC, VGS = 4.5V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM
20
20
20
20
Figure 4
A
A
A
A
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UIS Figures 6, 17, 18
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD
Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
0.74 W
W/oC
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG -55 to 175 oC
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL
Package Body for 10s, See Techbrief TB334. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg
300
260
oC
oC
NOTES:
1. TJ = 25oC to 150oC.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Data Sheet December 2001
©2001 Fairchild Semiconductor Corporation HUF76629D3, HUF76629D3S Rev. B
Electrical Specifications TC = 25oC, Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage BVDSS ID = 250µA, VGS = 0V (Figure 12) 100 - - V
ID = 250µA, VGS = 0V , TC = -40oC (Figure 12) 90 - - V
Zero Gate Voltage Drain Current IDSS VDS = 95V, VGS = 0V - - 1 µA
VDS = 90V, VGS = 0V, TC = 150oC - - 250 µA
Gate to Source Leakage Current IGSS VGS = ±16V - - ±100 nA
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA (Figure 11) 1 - 3 V
Drain to Source On Resistance rDS(ON) ID = 20A, VGS = 10V (Figures 9, 10) - 0.0415 0.052
ID = 20A, VGS = 5V (Figure 9) - 0.046 0.054
ID = 20A, VGS = 4.5V (Figure 9) - 0.047 0.055
THERMAL SPECIFICATIONS
Thermal Resistance Junction to Case RθJC TO-251AA and TO-252AA - - 1.36 oC/W
Thermal Resistance Junction to
Ambient RθJA - - 100 oC/W
SWITCHING SPECIFICATIONS (VGS = 4.5V)
Turn-On Time tON VDD = 50V, ID = 20A
VGS = 4.5V, RGS = 6.8
(Figures 15, 21, 22)
- - 190 ns
Turn-On Delay Time td(ON) -11-ns
Rise Time tr- 114 - ns
Turn-Off Delay Time td(OFF) -38-ns
Fall Time tf-60-ns
Turn-Off Time tOFF - - 145 ns
SWITCHING SPECIFICATIONS (VGS = 10V)
Turn-On Time tON VDD = 50V, ID = 20A
VGS = 10V,RGS = 8.2
(Figures 16, 21, 22)
- - 50 ns
Turn-On Delay Time td(ON) -6.8-ns
Rise Time tr-28-ns
Turn-Off Delay Time td(OFF) -67-ns
Fall Time tf-60-ns
Turn-Off Time tOFF - - 190 ns
GATE CHARGE SPECIFICATIONS
Total Gate Charge Qg(TOT) VGS = 0V to 10V VDD = 50V,
ID = 20A,
Ig(REF) = 1.0mA
(Figures 14, 19, 20)
-3846nC
Gate Charge at 5V Qg(5) VGS = 0V to 5V - 21 25 nC
Threshold Gate Charge Qg(TH) VGS = 0V to 1V - 1.2 1.6 nC
Gate to Source Gate Charge Qgs -3.3-nC
Gate to Drain "Miller" Charge Qgd -10-nC
CAPACITANCE SPECIFICATIONS
Input Capacitance CISS VDS = 25V, VGS = 0V,
f = 1MHz
(Figure 13)
- 1285 - pF
Output Capacitance COSS - 270 - pF
Reverse Transfer Capacitance CRSS -65-pF
Source to Drain Diode Specifications
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Source to Drain Diode Voltage VSD ISD = 20A - - 1.25 V
ISD = 10A - - 1.00 V
Reverse Recovery Time trr ISD = 20A, dISD/dt = 100A/µs - - 110 ns
Reverse Recovered Charge QRR ISD = 20A, dISD/dt = 100A/µs - - 370 nC
HUF76629D3, HUF76629D3S
©2001 Fairchild Semiconductor Corporation HUF76629D3, HUF76629D3S Rev. B
Typical Performance Curves
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
FIGURE 4. PEAK CURRENT CAPABILITY
TC, CASE TEMPERATURE (oC)
POWER DISSIPATION MULTIPLIER
00 25 50 75 100 17
5
0.2
0.4
0.6
0.8
1.0
1.2
125 150
25
15
20
50 75 100 125 150
025
I
D
, DRAIN CURRENT (A)
TC, CASE TEMPERATURE (oC)
VGS = 4.5V
VGS = 10V
17
5
5
10
0.1
1
2
10-4 10-3 10-2 10-1 100101
0.01
10-5
t, RECTANGULAR PULSE DURATION (s)
ZθJC, NORMALIZED
THERMAL IMPEDANCE
SINGLE PULSE NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
PDM
t1t2
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.01
0.02
100
600
10
10-4 10-3 10-2 10-1 100101
10-5
IDM, PEAK CURRENT (A)
t, PULSE WIDTH (s)
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
TC = 25oC
I = I25 175 - TC
150
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
VGS = 5V
VGS = 10V
HUF76629D3, HUF76629D3S
/// ////
©2001 Fairchild Semiconductor Corporation HUF76629D3, HUF76629D3S Rev. B
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
CAPABILITY
FIGURE 7. TRANSFER CHARACTERISTICS FIGURE 8. SATURATION CHARACTERISTICS
FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT FIGURE 10. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
Typical Performance Curves (Continued)
10
100
10 30
0
300
1
1
100µs
10ms
1ms
VDS, DRAIN TO SOURCE VOLTAGE (V)
ID, DRAIN CURRENT (A)
TC = 25oC
TJ = MAX RATED
SINGLE PULSE
LIMITED BY rDS(ON)
AREA MAY BE
OPERATION IN THIS
100
10
100
0.001 0.01 0.1
1
IAS, AVALANCHE CURRENT (A)
tAV, TIME IN AVALANCHE (ms)
STARTING TJ = 25oC
STARTING TJ = 150oC
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R = 0
If R 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
50
0
10
20
30
40
1.522.533.5 4.
5
ID, DRAIN CURRENT (A)
VGS, GATE TO SOURCE VOLTAGE (V)
TJ= 25oC
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 15V
TJ= 175oC
TJ= -55oC
4
50
0
10
20
30
40
0123
4
ID, DRAIN CURRENT (A)
VDS, DRAIN TO SOURCE VOLTAGE (V)
VGS = 3V
VGS = 3.5V
VGS = 5V
VGS = 10V
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
TC = 25oC
VGS = 4V
ID = 10A
30
40
50
60
24681
0
VGS, GATE TO SOURCE VOLTAGE (V)
ID = 20A
rDS(ON), DRAIN TO SOURCE
ON RESISTANCE (m)
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
TC = 25oC
0.5
1.0
1.5
2.0
3.0
-80 -40 0 40 80 120 20
0
NORMALIZED DRAIN TO SOURCE
TJ, JUNCTION TEMPERATURE (oC)
ON RESISTANCE
VGS = 10V, ID = 20A
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
160
2.5
HUF76629D3, HUF76629D3S
©2001 Fairchild Semiconductor Corporation HUF76629D3, HUF76629D3S Rev. B
FIGURE 11. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.
FIGURE 14. GATE CHARGE WAVEFORMS FOR CONSTANT
GATE CURRENT
FIGURE 15. SWITCHING TIME vs GATE RESISTANCE FIGURE 16. SWITCHING TIME vs GATE RESISTANCE
Typical Performance Curves (Continued)
0.4
0.8
1.0
1.4
-80 -40 0 40 80 120 200
NORMALIZED GATE
TJ, JUNCTION TEMPERATURE (oC)
VGS = VDS, ID = 250µA
THRESHOLD VOLTAGE
0.6
160
1.2
0.9
1.0
1.1
1.2
-80 -40 0 40 80 120 200
TJ, JUNCTION TEMPERATURE (oC)
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
ID = 250µA
160160
10
100
1000
3000
0.1 1.0 10 10
0
C, CAPACITANCE (pF)
VDS, DRAIN TO SOURCE VOLTAGE (V)
VGS = 0V, f = 1MHz
CISS = CGS + CGD
COSS CDS + CGD
CRSS = CGD
0
2
4
6
8
10
01020304
0
VGS, GATE TO SOURCE VOLTAGE (V)
VDD = 50V
Qg, GATE CHARGE (nC)
ID = 20A
ID = 10A
WAVEFORMS IN
DESCENDING ORDER:
50
100
250
0 1020304050
0
SWITCHING TIME (ns)
RGS, GATE TO SOURCE RESISTANCE ()
VGS = 4.5V, VDD = 50V, ID = 20A
tr
tf
td(ON)
td(OFF)
150
200
100
200
300
0 1020304050
0
SWITCHING TIME (ns)
RGS, GATE TO SOURCE RESISTANCE ()
VGS = 10V, VDD = 50V, ID = 20A
td(OFF)
tr
td(ON)
tf
50
150
250
HUF76629D3, HUF76629D3S
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©2001 Fairchild Semiconductor Corporation HUF76629D3, HUF76629D3S Rev. B
Test Circuits and Waveforms
FIGURE 17. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 18. UNCLAMPED ENERGY WAVEFORMS
FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 20. GATE CHARGE WAVEFORMS
FIGURE 21. SWITCHING TIME TEST CIRCUIT FIGURE 22. SWITCHING TIME WAVEFORM
tP
VGS
0.01
L
IAS
+
-
VDS
VDD
RG
DUT
VARY tP TO OBTAIN
REQUIRED PEAK IAS
0V
VDD
VDS
BVDSS
tP
IAS
tAV
0
RL
VGS +
-
VDS
VDD
DUT
Ig(REF)
VDD
Qg(TH)
VGS = 1V
Qg(5)
VGS = 5V
Qg(TOT)
VGS = 10
V
VDS
VGS
I
g(REF)
0
0
Qgs Qgd
VGS
RL
RGS
DUT
+
-VDD
VDS
VGS
tON
td(ON)
tr
90%
10%
VDS 90%
10%
tf
td(OFF)
tOFF
90%
50%
50%
10% PULSE WIDTH
VGS
0
0
HUF76629D3, HUF76629D3S
1E| . rm @lT
©2001 Fairchild Semiconductor Corporation HUF76629D3, HUF76629D3S Rev. B
PSPICE Electrical Model
.SUBCKT HUF76629D3 2 1 3 ; rev 30 July 1999
CA 12 8 2.32e-9
CB 15 14 2.32e-9
CIN 6 8 1.22e-9
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
EBREAK 11 7 17 18 117.89
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
IT 8 17 1
LDRAIN 2 5 1e-9
LGATE 1 9 3.11e-9
LSOURCE 3 7 3.72e-9
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 2.97e-2
RGATE 9 20 2.81
RLDRAIN 2 5 10
RLGATE 1 9 54.2
RLSOURCE 3 7 41.6
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 6.5e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*61),3))}
.MODEL DBODYMOD D (IS = 1.15e-12 IKF = 4.3 RS = 7.45e-3 TRS1 = 2.40e-3 TRS2 = 5.15e-7 CJO = 1.14e-9 TT = 5.86e-8 M = 0.52 XTI = 3.65)
.MODEL DBREAKMOD D (RS = 3.78e- 1TRS1 = 1e- 3TRS2 = -1e-6)
.MODEL DPLCAPMOD D (CJO = 1.37e- 9IS = 1e-3 0N = 10 M = 0.94)
.MODEL MMEDMOD NMOS (VTO = 1.84 KP = 2.6 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 2.81)
.MODEL MSTROMOD NMOS (VTO = 2.13 KP = 42.5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 1.58 KP = 0.07 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 28.1 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 9.88e- 4TC2 = -5.40e-7)
.MODEL RDRAINMOD RES (TC1 = 7.85e-3 TC2 = 1.95e-5)
.MODEL RSLCMOD RES (TC1 = 4.97e-3 TC2 = 5.05e-6)
.MODEL RSOURCEMOD RES (TC1 = 1.5e-3 TC2 = 1e-6)
.MODEL RVTHRESMOD RES (TC1 = -1.85e-3 TC2 = -4.48e-6)
.MODEL RVTEMPMOD RES (TC1 = -1.72e- 3TC2 = 6.00e-7)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -5.5 VOFF= -2.2)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.2 VOFF= -5.5)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -1.1 VOFF= 0.5)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.5 VOFF= -1.1)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
18
22
+-
6
8
+
-
5
51
+
-
19
8
+-
17
18
6
8
+
-
5
8+
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17 18
19
22
12
13
15
S1A
S1B
S2A
S2B
CA CB
EGS EDS
14
8
13
814
13
MWEAK
EBREAK DBODY
RSOURCE
SOURCE
11
73
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES 16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ESLC
RSLC1
10
5
51
50
RSLC2
1
GATE RGATE EVTEMP
9
ESG
LGATE
RLGATE 20
+
-
+
-
+
-
6
HUF76629D3, HUF76629D3S
gw| w PM VII—I @lT
©2001 Fairchild Semiconductor Corporation HUF76629D3, HUF76629D3S Rev. B
SABER Electrical Model
REV 30 July 1999
template huf76629d3 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
d..model dbodymod = (is = 1.15e-12, cjo = 1.14e-9, tt = 5.86e-8, xti = 3.65, m = 0.52)
d..model dbreakmod = ()
d..model dplcapmod = (cjo = 1.37e-9, is = 1e-30, n = 10, m = 0.94)
m..model mmedmod = (type=_n, vto = 1.84, kp = 2.6, is = 1e-30, tox = 1)
m..model mstrongmod = (type=_n, vto = 2.13, kp = 42.5, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 1.58, kp = 0.07, is = 1e-30, tox = 1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -5.5, voff = -2.2)
sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -2.2, voff = -5.5)
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -1.1, voff = 0.5)
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.5, voff = -1.1)
c.ca n12 n8 = 2.32e-9
c.cb n15 n14 = 2.32e-9
c.cin n6 n8 = 1.22e-9
d.dbody n7 n71 = model=dbodymod
d.dbreak n72 n11 = model=dbreakmod
d.dplcap n10 n5 = model=dplcapmod
i.it n8 n17 = 1
l.ldrain n2 n5 = 1e-9
l.lgate n1 n9 = 3.11e-9
l.lsource n3 n7 = 3.72e-9
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
res.rbreak n17 n18 = 1, tc1 = 9.88e-4, tc2 = -5.40e-7
res.rdbody n71 n5 = 7.45e-3, tc1 = 2.40e-3, tc2 = 5.15e-7
res.rdbreak n72 n5 = 3.78e-1, tc1 = 1.00e-3, tc2 = -1.00e-6
res.rdrain n50 n16 = 2.97e-2, tc1 = 7.85e-3, tc2 = 1.95e-5
res.rgate n9 n20 = 2.81
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 54.2
res.rlsource n3 n7 = 41.6
res.rslc1 n5 n51 = 1e-6, tc1 = 4.97e-3, tc2 = 5.05e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 6.5e-3, tc1 = 1.5e-3, tc2 = 1e-6
res.rvtemp n18 n19 = 1, tc1 = -1.72e-3, tc2 = 6.00e-7
res.rvthres n22 n8 = 1, tc1 = -1.85e-3, tc2 = -4.48e-6
spe.ebreak n11 n7 n17 n18 = 117.89
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/61))** 3))
}
}
18
22
+-
6
8
+
-
19
8
+-
17
18
6
8
+
-
5
8+
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17 18
19
22
12
13
15
S1A
S1B
S2A
S2B
CA CB
EGS EDS
14
8
13
814
13
MWEAK
EBREAK DBODY
RSOURCE
SOURCE
11
73
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES 16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ISCL
RSLC1
10
5
51
50
RSLC2
1
GATE RGATE EVTEMP
9
ESG
LGATE
RLGATE 20
+
-
+
-
+
-
6
RDBODY
RDBREAK
72
71
HUF76629D3, HUF76629D3S
©2001 Fairchild Semiconductor Corporation HUF76629D3, HUF76629D3S Rev. B
SPICE Thermal Model
REV 26 July 1999
HUF76629D3
CTHERM1 th 6 2.45e-3
CTHERM2 6 5 8.15e-3
CTHERM3 5 4 7.40e-3
CTHERM4 4 3 7.45e-3
CTHERM5 3 2 1.01e-2
CTHERM6 2 tl 7.49e-2
RTHERM1 th 6 9.00e-3
RTHERM2 6 5 1.80e-2
RTHERM3 5 4 9.15e-2
RTHERM4 4 3 2.43e-1
RTHERM5 3 2 3.50e-1
RTHERM6 2 tl 3.62e-1
SABER Thermal Model
SABER thermal model HUF76629D3
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 = 2.45e-3
ctherm.ctherm2 6 5 = 8.15e-3
ctherm.ctherm3 5 4 = 7.40e-3
ctherm.ctherm4 4 3 = 7.45e-3
ctherm.ctherm5 3 2 = 1.01e-2
ctherm.ctherm6 2 tl = 7.49e-2
rtherm.rtherm1 th 6 = 9.00e-3
rtherm.rtherm2 6 5 = 1.80e-2
rtherm.rtherm3 5 4 = 9.15e-2
rtherm.rtherm4 4 3 = 2.43e-1
rtherm.rtherm5 3 2 = 3.50e-1
rtherm.rtherm6 2 tl = 3.62e-1
}
RTHERM4
RTHERM6
RTHERM5
RTHERM3
RTHERM2
RTHERM1
CTHERM4
CTHERM6
CTHERM5
CTHERM3
CTHERM2
CTHERM1
tl
2
3
4
5
6
th JUNCTION
CASE
HUF76629D3, HUF76629D3S
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