Details, datasheet, quote on part number: HM4-65642883
| Part | HM4-65642883 |
| Category | |
| Description | 8k X 8 Asynchronous CMOS Static RAM |
| Company | Intersil Corporation |
| Datasheet | Download HM4-65642883 Datasheet |
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| Quote |
| Features, Applications |
Description The is a CMOS x 8-bit Static Random Access Memory. The pinout is the JEDEC 28 pin, 8-bit wide standard, which allows easy memory board layouts which accommodate a variety of industry standard ROM, PROM, EPROM, EEPROM and RAMs. The HM-65642/883 is ideally suited for use in microprocessor based systems. In particular, interfacing with the Intersil 80C86 and 80C88 microprocessors is simplified by the convenient output enable (G) input. The is a full CMOS RAM which utilizes an array of six transistor (6T) memory cells for the most stable and lowest possible standby supply current over the full military temperature range. In addition to this, the high stability of the 6T RAM cell provides excellent protection against soft errors due to noise and alpha particles. This stability also improves the radiation tolerance of the RAM over that of four transistor or MIX-MOS (4T) devices FeaturesThis Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. Full CMOS Design Six Transistor Memory Cell Low Standby Supply Current.100�A Low Operating Supply Current. 20mA Fast Address Access Time. 150ns Low Data Retention Supply Voltage. 2.0V CMOS/TTL Compatible Inputs/Outputs JEDEC Approved Pinout Equal Cycle and Access Times No Clocks or Strobes Required Gated Inputs - No Pull-Up or Pull-Down Resistors Required Temperature Range to +125oC Easy Microprocessor Interfacing Dual Chip Enable Control PACKAGE CERDIP CLCC TEMPERATURE RANGE 200ns/250�A HM1-65642C/883 PKG. NO. F28.6 J32.ADESCRIPTION Address Input Data Input/Output Chip Enable Chip Enable Write Enable Output Enable No Connections Ground Power CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com 407-727-9207 | Copyright � Intersil Corporation 1999 Supply Voltage. +7.0V Input or Output Voltage Applied for all Grades.GND -0.3V to VCC +0.3V Typical Derating Factor. 5mA/MHz Increase in ICCOP ESD Classification. Class 1 Thermal Resistance (Typical) JA JC CERDIP Package. 45oC/W 8oC/W CLCC Package. 55oC/W 10oC/W Maximum Storage Temperature to +150oC Maximum Junction Temperature. +175oC Maximum Lead Temperature (Soldering 10s). +300oC CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Operating Voltage Range. to +5.5V Operating Temperature Range. to +125oC Input Low Voltage. to +0.8V Input High Voltage. +2.2V to VCC +0.3V Data Retention Supply Voltage. 2.0V Input Rise and Fall Time. 40ns Max. TABLE HM-65642/883 DC ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested LIMITS PARAMETER High Level Output Voltage Low Level Output Voltage High Impedance Output Leakage Current SYMBOL VOH 1 (NOTE 1) CONDITIONS VCC = -1.0mA GROUP A SUBGROUPS 2, 3 TEMPERATURE TA +125oC MIN 2.4 MAX UNITS V Standby Supply Current Enable Supply Current Operating Supply Current TABLE HM-65642/883 DC ELECTRICAL PERFORMANCE SPECIFICATIONS (Continued) Device Guaranteed and 100% Tested LIMITS PARAMETER Data Retention Supply Current SYMBOL ICCDR (NOTE 1) CONDITIONS HM-65642B/883 VCC E1 = VCC E2 = GND +0.3V HM-65642/883 VCC E1 = VCC E2 = GND +0.3V HM-65642C/883 VCC E1 = VCC E2 = GND +0.3V Functional Test NOTES: 1. All voltages referenced to device GND. 2. Typical derating 5mA/MHz increase in ICCOP. 3. Tested as follows: = 2MHz, VIH = 2.4V, VIL = 0.4V, IOH = -4.0mA, IOL = 4.0mA, VOH 1.5V, and VOL 1.5V. TABLE HM-65642/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS PARAMETERS Read/Write/ Cycle Time Address Access Time Output Enable Access Time Chip Enable Access Time Write Recovery Time Chip Enable to End-of-Write Address Setup Time Write Enable Pulse Width Data Setup Time |
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